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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics.
v850e/ma2 32-bit single-chip microcontroller hardware user?s manual pd703108 printed in japan document no. u14980ej2v1ud00 (2nd edition) date published august 2005 n cp(k) 2000
2 user's manual u14980ej2v1ud [memo]
3 user's manual u14980ej2v1ud 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
4 user's manual u14980ej2v1ud windows is either a registered tradem ark or a trademark of microsoft cor poration in the united states and/or other countries. the information in this document is current as of july, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
5 user's manual u14980ej2v1ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j05.6 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 v?lizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-265 40 10 ? tyskland filial taeby, sweden tel: 08-63 87 200 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
6 user's manual u14980ej2v1ud major revisions in this edition (1/4) page description throughout ? deletion of busclk pin ? deletion of bus cycle period control register (b cp) and port cm function control register (pfccm) p.27 deletion of note from 1.4 ordering information p.37 addition of note to 2.2 pin status p.39 modification of description in 2.3 (3) (b) (iii) tc0 (terminal count) p.41 modification of description in 2.3 (7) (b) (i) wait (wait) p.44 addition of description to 2.3 (10) (b) (ii) sdclk (sdram clock output) p.58 modification of caution in 3.4.3 (1) program space p.62 modification of description in and addition of caution to 3.4.5 (2) internal ram area p.63 addition of note to 3.4.5 (3) internal peripheral i/o area p.66 modification of bit units for manipulation for dma terminal c ount output control register in 3.4.8 peripheral i/o registers p.72 modification of description in table and addition of remark to 3.4.10 system wait control register (vswc) p.74 modification of description in 4.2.1 pin status during internal ram and peripheral i/o access p.75 addition of note to 4.3 memory block function p.76 addition of caution to 4.3.1 chip select control function p.77 addition of description to 4.4 (1) bus cycle type configuration registers 0, 1 (bct0, bct1) p.79 modification of table in 4.5.1 number of access clocks p.79 addition of description to 4.5.2 (1) bus size configuration register (bsc) p.80 addition of caution to 4.5.3 (1) endian configuration register (bec) p.94 addition of caution to 4.6.1 (2) address setup wait control register (asc) p.100 addition of description to 4.8.1 function outline p.109 deletion of description from 4.10.1 program space p.124 addition of note to figure 5-5 page rom access timing (1/4) pp.131 and 132 modification of description for setting of ltm2n to ltm0n bits in and addition of caution to 5.3.4 sdram configuration registers 3, 4 (scr3, scr4) p.147 addition of caution to 5.3.6 (1) sdram refresh control registers 3, 4 (rfs3, rfs4) p.153 modification of description in and addition of note to figure 5-14 self refresh timing (sdram) p.159 addition of description to 6.3.1 (1) dma source address registers 0h to 3h (dsa0h to dsa3h) p.161 addition of description to 6.3.2 (1) dma destination address registers 0h to 3h (dda0h to dda3h) p.164 addition of caution to 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) p.166 modification of description in and addition of caution to 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) p.168 addition of description to 6.3.6 dma disable status register (ddis) p.168 addition of description to 6.3.7 dma restart register (drst) p.169 modification of description in and addition of reserved word < > in device file to bits 3 to 0 to 6.3.8 dma terminal count output control register (dtoc) p.170 addition of caution to 6.3.9 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) p.170 addition of description and figure to 6.5.1 single transfer mode
7 user's manual u14980ej2v1ud major revisions in this edition (2/4) page description p.177 addition of description to 6.5.3 block transfer mode p.178 addition of caution to 6.6 two-cycle transfer p.188 modification of remark in 6.7.1 transfer type and transfer object p.189 addition of caution to 6.8 dma channel priorities p.191 addition of figure 6-14 terminal count signal (tc0) output example p.193 addition of description to remark in figure 6-16 example of forcible termination of dma transfer p.194 modification of description in table 6-3 number of minimum execution clocks in dma cycle p.195 addition of description to and modification of description in 6.16 one-time transfer during single transfer via dmarq0, dmarq1 signals p.195 modification of figure 6-17 time to perform single transfer one time p.196 addition of 6.17 (4) maintenance of dmarqn signal p.196 addition of 6.17 (6) dma start factors p.201 modification of description in figure 7-2 acknowledging non-maskable interrupt request p.211 addition of caution to 7.3.4 interrupt control register (xxicn) p.213 addition of caution to and deletion of reserved word < > in device file from 7.3.5 interrupt mask registers 0 to 3 (imr0 to imr3) p.215 addition of caution to 7.3.6 in-service priority register (ispr) p.216 addition of caution to 7.3.9 (1) external interrupt mode registers 1, 2 (intm1, intm2) p.218 addition of caution to 7.3.9 (2) valid edge selection registers c0, c1 (sesc0, sesc1) p.228 modification of description in figure 7-14 pipeline operation at interrupt request acknowledgement (outline) p.229 modification of description in 7.8 periods in which interrupts are not acknowledged p.236 addition of description to 9.3.5 peripheral status register (phs) p.247 addition of description to 9.5.4 (2) (a) release by non-maskable interrupt request or unmasked maskable interrupt request p.250 addition of description to 9.5.5 (2) (a) release by non-maskable interrupt request or unmasked maskable interrupt request p.251 modification of figure in 9.6.1 (1) securing the time using an on-chip time base counter p.252 modification of figure in 9.6.1 (2) securing the time according to the signal level width (reset pin input) p.258 addition of caution to 10.1.4 (2) (a) setting these registers to capture registers (cmsn0 and cmsn1 of tmccn1 = 0) p.260 addition of caution to 10.1.5 (1) timer mode control registers c00, c10 (tmcc00, tmcc10) pp.262 and 263 change of bit name of bit 5 of tmcc01 register in 10.1.5 (2) timer mode control registers c01, c11 (tmcc01, tmcc11) p.270 addition of figure 10-5 compare operation example (2/2) p.278 deletion of caution from and addition of note to figure 10-12 cycle measurement operation timing example p.283 modification of description in figure 10-13 example of timing during tmdn operation p.285 addition of caution to 10.2.5 (1) timer mode control registers d0 to d3 (tmcd0 to tmcd3)
8 user's manual u14980ej2v1ud major revisions in this edition (3/4) page description p.296 modification of description for pen bi t = 0, fen bit = 0, oven bit = 0 in 11.2.3 (2) asynchronous serial interface status registers 0, 1 (asis0, asis1) p.297 modification of description for txbfn bit, txsfn bit in 11.2.3 (3) asynchronous serial interface transmission status registers 0, 1 (asif0, asif1) p.304 modification of descripti on in and addition of figure to 11.2.5 (3) continuous transmission operation p.306 modification of description in and addition of note to figure 11-5 continuous transmission starting procedure p.307 modification of description in figure 11-6 continuous transmission ending procedure p.309 modification of figure and addition of caution to figure 11-7 asynchronous serial interface reception completion interrupt timing p.314 addition of caution to 11.2.6 (2) (a) clock select registers 0, 1 (cksr0, cksr1) p.320 addition of (2) to 11.2.7 precautions p.322 addition of description to 11.3.3 (1) clocked serial interface mode registers 0, 1 (csim0, csim1) p.334 addition of description to 12.2 (5) successive approximation register (sar) p.338 addition of caution to 12.3 (2) a/d converter mode register 1 (adm1) p.340 change of bit names in 12.3 (4) a/d conversion result registers (adcr0 to adcr3, adcr0h to adcr3h) p.343 addition of description to 12.4.2 (1) (b) timer trigger mode p.345 modification of figure 12-3 select mode operation timing: 1-buffer mode (ani1) p.346 modification of figure 12-4 select mode operation timing: 4-buffer mode (ani2) p.347 modification of figure 12-5 scan mode operation timing: 4-channel scan (ani0 to ani3) p.359 addition of 12.7.5 reconversion operations in timer 1 trigger mode p.360 addition of 12.7.6 supplementary information on a/d conversion time p.362 addition of 12.8 how to read a/d converter characteristics table pp.368 and 369 modification of bl ock type in and addition of caution to 13.2 (1) function of each port p.370 modification of register that sets the mode of port cm in 13.2 (2) function when each port?s pins are reset and registers that set the port/control mode p.373 modification of figure 13-4 block diagram of type d p.374 addition of figure 13-6 block diagram of type g p.375 modification of figure 13-7 block diagram of type h p.378 modification of figure 13-10 block diagram of type m p.379 modification of figure 13-11 block diagram of type n p.382 partial deletion of description from pmc0n bit = 0 in 13.3.1 (2) (b) port 0 mode control register (pmc0) p.387 partial deletion of description from pmc24 bit = 0 in 13.3.3 (2) (b) port 2 mode control register (pmc2) p.388 modification of block type of p40 and p43 in 13.3.4 (1) operation in control mode p.391 addition of caution to 13.3.5 (1) operation in control mode p.397 addition of caution to 13.3.8 (2) (b) port dl mode control register (pmcdl) p.402 modification of block type of pcm1 in 13.3.11 (1) operation in control mode p.409 addition of pin status of lbe and ube pins to table 14-1 operation status of each pin during reset
9 user's manual u14980ej2v1ud major revisions in this edition (4/4) page description p.414 addition of chapter 15 electrical specifications p.444 addition of chapter 16 package drawing p.445 addition of chapter 17 recommended soldering conditions p.446 addition of appendix a notes on target system design p.447 addition of appendix b cautions pp.457 to 462 modification of description in d.2 instruction set (in alphabetical order) major revisions in modifica tion version (u14980ej2v1ud00) p.27 modification of 1.4 ordering information p.28 addition of description to 1.5 pin configuration (top view) p.445 modification of chapter 17 recommended soldering conditions the mark shows major revised points.
10 user's manual u14980ej2v1ud introduction readers this manual is intended for users who wish to understand the functions of the v850e/ma2 ( pd703108) to design application systems using the v850e/ma2. purpose the purpose of this manual is for us ers to gain an understanding of the hardware functions of the ve850e/ma2. organization the v850e/ma2 user?s manual is divided into two parts: hardware (this manual) and architecture (v850e1 user?s manual architecture) . the organization of each manual is as follows: hardware architecture ? pin functions ? data type ? cpu function ? register set ? internal peripheral functions ? instruction format and instruction set ? electrical specifications ? interrupt and exception ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. ? to find the details of a regi ster where the name is known refer to appendix c register index . ? to find the details of a functi on, etc. where the name is known refer to appendix e index . ? to understand the details of an instruction function refer to the v850e1 user?s manual architecture . ? to know the electrical spec ifications of the v850e/ma2 refer to chapter 15 electrical specifications. ? to understand the overall f unctions of the v850e/ma2 read this manual according to the contents. ? how to interpret the register format for the bit whose bit number is enclosed in brackets, its bit name is defined as a reserved word in the device file.
11 user's manual u14980ej2v1ud conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: top: higher, bottom: lower note: footnote for item marked with note in the text caution: information requiring particular attention remark: supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 data type: word ... 32 bits halfword ... 16 bits byte ... 8 bits related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850e/ma2 document name document no. v850e1 architecture user?s manual u14559e v850e/ma2 hardware user?s manual this manual
12 user's manual u14980ej2v1ud documents related to developm ent tools (user?s manuals) document name document no. ie-v850e-mc, ie-v850e-mc-a (i n-circuit emulator) u14487e ie-703107-mc-em1 (in-circuit em ulator option board) u14481e operation u14568e c language u14566e project manager u14569e ca850 (ver.2.30 or later) (c compiler package) assembly language u14567e operation u15024e c language u15025e project manager u15026e ca850 (ver.2.40 or later) (c compiler package) assembly language u15027e id850 (ver.2.40) (integrated debugger) operation windows tm based u15181e sm850 (ver.2.40) (system simulato r) operation windows based u15182e sm850 (ver.2.00 or later) (system simulato r) external part user open interface specification u14873e basics u13430e installation u13410e rx850 (ver.3.13 or later) (real-time os) technical u13431e basics u13773e installation u13774e rx850 pro (ver.3.13) (real-time os) technical u13772e rd850 (ver.3.01) (task debugger) u13737e rd850 pro (ver.3.01) (task debugger) u13916e az850 (ver.3.0) (system performance analyzer) u14410e
user's manual u14980ej2v1ud 13 contents chapter 1 intro duction ...................................................................................................... ..........................24 1.1 outline.................................................................................................................... ...................................24 1.2 feat ures ................................................................................................................... .................................25 1.3 appli cations ............................................................................................................... ..............................27 1.4 ordering in formation ....................................................................................................... ........................27 1.5 pin configuration (top view) ............................................................................................... ...................28 1.6 function block ............................................................................................................. ............................30 1.6.1 internal block di agram................................................................................................... ...............30 1.6.2 on-chi p units............................................................................................................ ....................31 chapter 2 pi n funct ions.................................................................................................... ...........................33 2.1 list of pin function....................................................................................................... ...........................33 2.2 pin status ................................................................................................................. ................................37 2.3 description of pin functions ............................................................................................... ...................38 2.4 pin i/o circuits and recomme nded connection of unused pins........................................................47 2.5 pin i/o circuits ........................................................................................................... ..............................49 chapter 3 cpu f unction..................................................................................................... ...........................50 3.1 feat ures ................................................................................................................... .................................50 3.2 cpu regi ster set........................................................................................................... ...........................51 3.2.1 program re gister set ..................................................................................................... ...............52 3.2.2 system r egister set ...................................................................................................... ................53 3.3 operati on modes............................................................................................................ ..........................55 3.3.1 operat ion mo des .......................................................................................................... ...............55 3.3.2 operation mode specific ation............................................................................................. ..........55 3.4 address space .............................................................................................................. ...........................56 3.4.1 cpu addr ess s pace ........................................................................................................ .............56 3.4.2 image .................................................................................................................... .......................57 3.4.3 wrap-around of cpu address space ......................................................................................... ..58 3.4.4 memo ry map ............................................................................................................... .................59 3.4.5 area ..................................................................................................................... ........................60 3.4.6 external me mory ex pansio n................................................................................................ .........64 3.4.7 recommended us e of addres s space......................................................................................... .65 3.4.8 peripheral i/o registers ................................................................................................. ...............66 3.4.9 specific registers....................................................................................................... ...................72 3.4.10 system wait co ntrol regist er (vswc)..................................................................................... ......72 3.4.11 c autio ns................................................................................................................ .......................72 chapter 4 bus control function ............................................................................................ ................73 4.1 feat ures ................................................................................................................... .................................73 4.2 bus cont rol pins ........................................................................................................... ...........................74 4.2.1 pin status during internal ram and periphera l i/o acce ss ...........................................................74 4.3 memory bl ock function ...................................................................................................... ....................75 4.3.1 chip select control f unction ............................................................................................. .............76 4.4 bus cycle type control function............................................................................................ ...............77
user's manual u14980ej2v1ud 14 4.5 bus acc ess ................................................................................................................. ..............................79 4.5.1 number of access clocks .................................................................................................. ...........79 4.5.2 bus sizi ng func tion ...................................................................................................... .................79 4.5.3 endian cont rol func tion.................................................................................................. ...............80 4.5.4 big endian method usage restrictions in nec electronics development tools ..............................81 4.5.5 bu s width................................................................................................................ ......................83 4.6 wait function.............................................................................................................. ..............................94 4.6.1 programmable wait f unction............................................................................................... ..........94 4.6.2 external wait function ................................................................................................... ................97 4.6.3 relationship betw een programmable wait and external wait........................................................97 4.6.4 bus cycles in which wait function is valid ............................................................................... ......98 4.7 idle state in sertion function .............................................................................................. .....................99 4.8 bus hold function .......................................................................................................... .......................100 4.8.1 functi on out line........................................................................................................ ..................100 4.8.2 bus hold proce dure ....................................................................................................... .............101 4.8.3 operation in power sa ve mode ............................................................................................ ......101 4.8.4 bus hold ti ming (sram) ................................................................................................... ..........102 4.8.5 bus hold ti ming (sdram) .................................................................................................. ........104 4.9 bus priori ty order ......................................................................................................... .........................108 4.10 boundary oper ation conditions ............................................................................................. ..............109 4.10.1 progr am space.......................................................................................................... .................109 4.10.2 data space .............................................................................................................. ...................109 chapter 5 memory acc ess control function................................................................................. 110 5.1 sram, external rom, external i/o interface................................................................................. .......110 5.1.1 f eatur es ................................................................................................................. ....................110 5.1.2 sram connec tion ......................................................................................................... .............111 5.1.3 sram, external ro m, external i/o access ................................................................................1 13 5.2 page rom c ontroller (romc) ................................................................................................. ..............119 5.2.1 f eatur es ................................................................................................................. ....................119 5.2.2 page ro m connec tion ...................................................................................................... .........120 5.2.3 on-page/o ff-page ju dgment ............................................................................................... ........121 5.2.4 page rom configur ation regist er (prc) ................................................................................... .123 5.2.5 page ro m access .......................................................................................................... ...........124 5.3 sdram c ontroller ........................................................................................................... .......................128 5.3.1 f eatur es ................................................................................................................ .....................128 5.3.2 sdram connec tion ........................................................................................................ ............128 5.3.3 address mult iplex function ............................................................................................... ..........129 5.3.4 sdram configur ation registers 3, 4 (scr3, s cr4) ................................................................... 131 5.3.5 sdra m access ............................................................................................................ ..............133 5.3.6 refresh co ntrol f unction ................................................................................................. ............147 5.3.7 self-refresh control f unction ............................................................................................ ...........152 5.3.8 sdram initia lization se quence ............................................................................................ ......154 chapter 6 dma function s (dma controller)................................................................................. ...157 6.1 feat ures ................................................................................................................... ...............................157 6.2 confi guration.............................................................................................................. ............................158 6.3 control regist ers .......................................................................................................... .........................159
user's manual u14980ej2v1ud 15 6.3.1 dma source address regist ers 0 to 3 (dsa0 to d sa3) ..............................................................159 6.3.2 dma destination address regi sters 0 to 3 ( dda0 to dda3) .......................................................161 6.3.3 dma byte count register s 0 to 3 (dbc0 to dbc3 ) ..................................................................... 163 6.3.4 dma addressing control register s 0 to 3 (dadc0 to da dc3) ....................................................164 6.3.5 dma channel control regist ers 0 to 3 (dchc 0 to dchc3 ) ........................................................166 6.3.6 dma disable stat us register (ddis) ....................................................................................... ....168 6.3.7 dma restart register (drst)............................................................................................. .........168 6.3.8 dma terminal count output control regist er (dto c) .................................................................. 169 6.3.9 dma trigger factor regist ers 0 to 3 (dtfr 0 to d tfr3) ..............................................................170 6.4 dma bu s stat es ............................................................................................................. ........................172 6.4.1 types of bus st ates...................................................................................................... ..............172 6.4.2 dmac bus cycle state tr ansition .......................................................................................... ......173 6.5 transfer modes ............................................................................................................. .........................174 6.5.1 single tr ansfer mode ..................................................................................................... .............174 6.5.2 single-step transfer mode ................................................................................................ ..........176 6.5.3 block transfer mode ..................................................................................................... ..............177 6.6 two-cycl e tran sfer......................................................................................................... .......................178 6.7 transfer object............................................................................................................ ...........................188 6.7.1 transfer type and transfe r object ....................................................................................... ........188 6.7.2 external bus cycles during dma transfer .................................................................................. .188 6.8 dma channe l priori ties ..................................................................................................... ....................189 6.9 next address setting function.............................................................................................. ...............189 6.10 dma transfer start f actors ................................................................................................ ..................190 6.11 terminal count output upon dma tran sfer end ............................................................................... .191 6.12 forcibl e interrupt ........................................................................................................ ...........................192 6.13 forcible termina tion...................................................................................................... ........................193 6.14 times related to dma tr ansfer ............................................................................................. ...............194 6.15 maximum response time for dma transf er requ est........................................................................ 194 6.16 one-time transfer during single transfer via dmarq0, dmarq1 si gnals ....................................195 6.17 cautions.................................................................................................................. ................................196 6.17.1 interrupt factors....................................................................................................... ...................196 6.18 dma tran sfer end.......................................................................................................... ........................196 chapter 7 interrupt/exception processing funct ion .................................................................197 7.1 feat ures ................................................................................................................... ...............................197 7.2 non-maskable interrupt ..................................................................................................... ....................199 7.2.1 oper ation ................................................................................................................ ...................200 7.2.2 re store .................................................................................................................. ....................202 7.2.3 non-maskable interr upt status flag (n p) .................................................................................. ..203 7.2.4 noise e liminat ion........................................................................................................ ................203 7.2.5 edge detect ion function .................................................................................................. ...........203 7.3 maskable interrupts ........................................................................................................ .......................204 7.3.1 oper ation ................................................................................................................ ...................204 7.3.2 re store .................................................................................................................. ....................206 7.3.3 priorities of maskable in terrupts........................................................................................ .........207 7.3.4 interrupt contro l register (xxicn) ....................................................................................... .........211 7.3.5 interrupt mask registers 0 to 3 (imr0 to imr3) ..........................................................................2 13 7.3.6 in-service priori ty register (ispr) ...................................................................................... .........215
user's manual u14980ej2v1ud 16 7.3.7 maskable interrupt status fl ag (id) ...................................................................................... .......215 7.3.8 noise e liminat ion ........................................................................................................ ................216 7.3.9 interrupt tri gger mode se lection......................................................................................... .........216 7.4 software exception ......................................................................................................... .......................219 7.4.1 oper ation ................................................................................................................ ...................219 7.4.2 re store.................................................................................................................. .....................220 7.4.3 exception status fl ag (ep) .............................................................................................. ............221 7.5 excepti on trap ............................................................................................................. ..........................222 7.5.1 illegal opc ode definit ion................................................................................................ ..............222 7.5.2 debu g tr ap ............................................................................................................... ..................224 7.6 multiple interrupt servicing control ....................................................................................... ..............226 7.7 interrupt latency time..................................................................................................... ......................228 7.8 periods in which interr upts are not a cknowledge d ..........................................................................2 29 chapter 8 prescal er unit (prs)............................................................................................ ..................230 chapter 9 clock generator function........................................................................................ ........231 9.1 feat ures ................................................................................................................... ...............................231 9.2 confi guration.............................................................................................................. ............................231 9.3 input clo ck select ion...................................................................................................... .......................232 9.3.1 direc t mode.............................................................................................................. ..................232 9.3.2 p ll mode................................................................................................................. ..................233 9.3.3 peripheral comm and register (phcmd).....................................................................................2 33 9.3.4 clock control register (ckc)............................................................................................. ..........234 9.3.5 peripheral stat us register (phs)......................................................................................... ........236 9.4 pll lockup................................................................................................................. ............................237 9.5 power s ave cont rol ......................................................................................................... ......................238 9.5.1 ov ervi ew ................................................................................................................. ...................238 9.5.2 control registers........................................................................................................ .................240 9.5.3 halt mode ................................................................................................................ ................243 9.5.4 idle mode ................................................................................................................ .................245 9.5.5 software stop mode ....................................................................................................... .........248 9.6 securing oscillation stabilization time .................................................................................... ...........251 9.6.1 oscillation stabilization ti me security s pecificat ion .................................................................... .251 9.6.2 time base counter (tbc) .................................................................................................. .........253 chapter 10 timer/counter function (real-time pulse un it)......................................................254 10.1 time r c................................................................................................................... .................................254 10.1.1 features (timer c) ...................................................................................................... ................254 10.1.2 function over view (tim er c) ............................................................................................. ..........254 10.1.3 basic configur ation of timer c .......................................................................................... ..........255 10.1.4 ti mer c ................................................................................................................. .....................256 10.1.5 timer c cont rol regi sters ............................................................................................... .............260 10.1.6 timer c operat ion ....................................................................................................... ...............265 10.1.7 application ex amples (timer c) .......................................................................................... ........272 10.1.8 precautions (timer c) ................................................................................................... ..............279 10.2 time r d................................................................................................................... .................................280 10.2.1 features (timer d) ...................................................................................................... ................280
user's manual u14980ej2v1ud 17 10.2.2 function over view (tim er d) ............................................................................................. ..........280 10.2.3 basic configur ation of timer d .......................................................................................... ..........280 10.2.4 ti mer d ................................................................................................................. .....................281 10.2.5 timer d cont rol regi sters............................................................................................... .............284 10.2.6 timer d operat ion ....................................................................................................... ...............286 10.2.7 application ex amples (timer d) .......................................................................................... ........288 10.2.8 precautions (timer d) ................................................................................................... ..............288 chapter 11 serial interface function...................................................................................... ..........289 11.1 feat ures .................................................................................................................. ................................289 11.1.1 switching between uart and cs i modes .................................................................................289 11.2 asynchronous serial inte rfaces 0, 1 (u art0, uart 1) .......................................................................2 90 11.2.1 f eatur es................................................................................................................ .....................290 11.2.2 config uration........................................................................................................... ...................291 11.2.3 control registers....................................................................................................... ..................293 11.2.4 interrupt requests...................................................................................................... .................300 11.2.5 oper ation ............................................................................................................... ....................301 11.2.6 dedicated baud rate gener ators 0, 1 (brg 0, brg1 ).................................................................313 11.2.7 prec auti ons ............................................................................................................. ...................320 11.3 clocked serial interf aces 0, 1 (csi 0, csi1) ............................................................................... ...........321 11.3.1 f eatur es................................................................................................................ .....................321 11.3.2 config uration........................................................................................................... ...................321 11.3.3 control registers....................................................................................................... ..................322 11.3.4 oper ation ............................................................................................................... ....................328 11.3.5 out put pi ns............................................................................................................. ....................331 11.3.6 system config uration ex ample ............................................................................................ .......332 chapter 12 a/ d converter ................................................................................................... ......................333 12.1 feat ures .................................................................................................................. ................................333 12.2 confi guration ............................................................................................................. ............................333 12.3 control regist ers ......................................................................................................... ..........................336 12.4 a/d converte r operation ................................................................................................... ....................342 12.4.1 basic operation of a/d c onverter ........................................................................................ .......342 12.4.2 operation mode and trigger mode ......................................................................................... ....343 12.5 operation in a/d trigge r mode ............................................................................................. ................348 12.5.1 select mo de operation ................................................................................................... ............348 12.5.2 scan mode operations .................................................................................................... ...........350 12.6 operation in ti mer trigge r mode........................................................................................... ...............351 12.6.1 select mo de operation ................................................................................................... ............352 12.6.2 scan mode operation..................................................................................................... ............356 12.7 precautions in operations ................................................................................................. ...................358 12.7.1 stopping conv ersion oper ation........................................................................................... ........358 12.7.2 timer tri gger inte rval .................................................................................................. ................358 12.7.3 operation in standby mode ............................................................................................... .........358 12.7.4 compare match interrupt wh en in timer tr igger m ode ................................................................ 359 12.7.5 reconversion operation in timer 1 tri gger m ode ........................................................................ 35 9 12.7.6 supplementary information on a/d conver sion ti me ..................................................................360 12.8 how to read a/d conver ter characteris tics ta ble ........................................................................... ..362
user's manual u14980ej2v1ud 18 chapter 13 po rt functions .................................................................................................. .....................366 13.1 feat ures .................................................................................................................. ................................366 13.2 port conf iguration........................................................................................................ ..........................367 13.3 port pin functions ........................................................................................................ .........................381 13.3.1 port 0.................................................................................................................. ........................381 13.3.2 port 1.................................................................................................................. ........................384 13.3.3 port 2.................................................................................................................. ........................386 13.3.4 port 4.................................................................................................................. ........................388 13.3.5 port 7.................................................................................................................. ........................391 13.3.6 po rt al ................................................................................................................. ......................392 13.3.7 po rt ah................................................................................................................. ......................394 13.3.8 po rt dl ................................................................................................................. ......................396 13.3.9 po rt cs................................................................................................................. ......................398 13.3.10 po rt ct................................................................................................................ .......................400 13.3.11 po rt cm ................................................................................................................ ......................402 13.3.12 po rt cd ................................................................................................................ ......................404 13.3.13 po rt bd................................................................................................................ .......................407 chapter 14 reset functions ................................................................................................. ....................409 14.1 feat ures .................................................................................................................. ................................409 14.2 pin functions............................................................................................................. .............................409 14.3 initia lization............................................................................................................ .................................411 chapter 15 electri cal specif ications ....................................................................................... ..........414 chapter 16 package drawing................................................................................................. ..................444 chapter 17 recommended soldering co ndition s ...........................................................................445 appendix a notes on target sys tem design................................................................................ ....446 appendix b cautions......................................................................................................... .............................447 b.1 restriction on page rom access............................................................................................. ............447 b.1.1 descr iption .............................................................................................................. ...................447 b.1.2 counte rmeasur es.......................................................................................................... .............448 appendix c re gister index .................................................................................................. .......................449 appendix d inst ruction set list ........................................................................................... ..................454 d.1 con ventions................................................................................................................ ............................454 d.2 instruction set (i n alphabetical order).................................................................................... .............457 appendix e index ............................................................................................................ .................................464
user's manual u14980ej2v1ud 19 list of figures (1/4) figure no. title page 3-1 cpu addr ess s pace.......................................................................................................... .............................56 3-2 images on a ddress space .................................................................................................... .........................57 3-3 memory map................................................................................................................. ..................................59 4-1 big endian addre sses within word........................................................................................... .....................81 4-2 little endian addr esses with in word ........................................................................................ .....................81 4-3 example of wa it insertion.................................................................................................. .............................97 5-1 examples of c onnection to sram ............................................................................................. ..................111 5-2 sram, external rom, external i/o a ccess ti ming............................................................................. .........113 5-3 examples of conn ection to page rom ......................................................................................... ...............120 5-4 on-page/off-page judgment duri ng page rom connecti on ......................................................................1 21 5-5 page rom ac cess ti ming ..................................................................................................... ......................124 5-6 example of co nnection to sdram............................................................................................. ..................128 5-7 row address/colu mn addre ss out put .......................................................................................... ...............129 5-8 state transition of sdram access ........................................................................................... ...................133 5-9 sdram single read c ycle .................................................................................................... ......................135 5-10 sdram single write cycle .................................................................................................. ........................139 5-11 sdram a ccess ti ming ....................................................................................................... .........................143 5-12 auto re fresh c ycle........................................................................................................ ...............................150 5-13 cbr refresh timing (sdram) ................................................................................................ ....................151 5-14 self refres h timing (sdram)............................................................................................... .......................153 5-15 sdram mode regist er setting cycle ......................................................................................... .................155 5-16 sdram register wr ite operati on timi ng..................................................................................... ................156 6-1 dmac bus cycle state trans ition............................................................................................ ....................173 6-2 single transfe r example 1 .................................................................................................. .........................174 6-3 single transfe r example 2 .................................................................................................. .........................174 6-4 single transfe r example 3 .................................................................................................. .........................175 6-5 single-step trans fer example 1............................................................................................. ......................176 6-6 single-step trans fer example 2............................................................................................. ......................176 6-7 block trans fer exam ple ..................................................................................................... ..........................177 6-8 timing of access to sram, external rom, a nd external i/o during 2- cycle dma tr ansfer .......................179 6-9 timing of 2-cycle dma transfer (external i/o sram ) ............................................................................181 6-10 timing of 2-cycle dma transfer (sram sdra m) .................................................................................. 182 6-11 timing of 2-cycle dma transfer (sdram sram ) ..................................................................................185 6-12 buffer register configur ation ............................................................................................. ..........................189 6-13 terminal count signal (tc0) timi ng example ................................................................................ .............191 6-14 example of terminal count signal (t c0) ou tput ............................................................................. ............191 6-15 example of forcible interrupt of dma trans fer ............................................................................. ...............192 6-16 example of forcible termination of dma trans fer........................................................................... ............193 6-17 time to perform si ngle transfer one time .................................................................................. ................195 7-1 servicing conf iguration of non -maskable in terrupt .......................................................................... ............200
user's manual u14980ej2v1ud 20 list of figures (2/4) figure no. title page 7-2 acknowledging non-maska ble interrupt request ............................................................................... ..........201 7-3 reti instruct ion proc essing ................................................................................................ .........................202 7-4 maskable interr upt serv icing ............................................................................................... .........................205 7-5 reti instruct ion proc essing ................................................................................................ .........................206 7-6 example of processing in which anothe r interrupt request is issued while an interrupt is be ing proc essed.................................................................................................. .......................208 7-7 example of processing interrupt requests simultaneo usly gener ated ........................................................21 0 7-8 software except ion proc essing .............................................................................................. ......................219 7-9 reti instruct ion proc essing ................................................................................................ .........................220 7-10 exception tr ap processing ................................................................................................. ..........................223 7-11 restore pr ocessing from e xception trap .................................................................................... .................223 7-12 debug tr ap proce ssing ..................................................................................................... ...........................224 7-13 restore processi ng from d ebug trap ........................................................................................ ..................225 7-14 pipeline oper ation at interrupt request acknowledgement (outline)......................................................... ..228 9-1 power save mode st ate transiti on diagr am ................................................................................... .............239 10-1 basic operatio n of ti mer c................................................................................................ ...........................265 10-2 operation after over flow (when os tn = 1) .................................................................................. ...............266 10-3 capture oper ation ex ample ................................................................................................. ........................267 10-4 tmc1 capture operation example (when both edges ar e specif ied) ........................................................268 10-5 compare oper ation ex ample ................................................................................................. ......................269 10-6 tmc0 compare operation exam ple (set/reset output mode) .................................................................... 271 10-7 contents of register settings when timer c is used as interval timer...................................................... .272 10-8 interval timer oper ation timing example................................................................................... ..................273 10-9 contents of register settings w hen timer c is used for pwm ou tput .......................................................27 4 10-10 pwm output timing ex ample................................................................................................ .......................275 10-11 contents of register settings when timer c is used for cycle meas urement ............................................277 10-12 cycle measurement o peration timi ng exam ple............................................................................... ............278 10-13 example of timing du ring tmdn o peration .................................................................................. ...............283 10-14 tmd0 compare o peration ex ample........................................................................................... ..................286 11-1 asynchronous serial interface bl ock dia gram............................................................................... ...............292 11-2 asynchronous serial interfac e transmit/receive data format ................................................................ ....301 11-3 asynchronous serial interface trans mission completion in terrupt ti ming...................................................3 03 11-4 continuous transmi ssion processi ng flow ................................................................................... ...............305 11-5 continuous transmissi on starting pr ocedure................................................................................ ...............306 11-6 continuous transmi ssion ending pr ocedure.................................................................................. ..............307 11-7 asynchronous serial interface rec eption completion interrupt timing ....................................................... .309 11-8 when reception error interrupt is separated from intsrn interrupt (isrmn bi t = 0) .................................310 11-9 when reception error interrupt is included in intsrn interrupt (isrmn bi t = 1).........................................310 11-10 noise filt er circuit ..................................................................................................... ...................................312 11-11 timing of rxdn sign al judged as noise .................................................................................... ..................312 11-12 baud rate generat or config uration ........................................................................................ .....................313
user's manual u14980ej2v1ud 21 list of figures (3/4) figure no. title page 11-13 allowable baud rate range during reception ............................................................................... .............318 11-14 transfer rate during continuous transmi ssion............................................................................. ..............320 11-15 clocked serial inte rface bloc k diagram ................................................................................... ....................322 11-16 transfe r timing .......................................................................................................... ..................................329 11-17 clock timing............................................................................................................. ....................................330 11-18 system configurat ion example of csi ...................................................................................... ...................332 12-1 block diagram of a/d conv erter............................................................................................ .......................335 12-2 relationship between analog input voltage and a/d conv ersion resu lts...................................................341 12-3 select mode operation timing: 1-buffe r mode (a ni1) ........................................................................ .........345 12-4 select mode operation timing: 4-buffe r mode (a ni2) ........................................................................ .........346 12-5 scan mode operation timing: 4-channel scan (a ni0 to ani3) ................................................................. ..347 12-6 example of 1-buffer mode (a/d tr igger select 1-bu ffer) oper ation .......................................................... ...348 12-7 example of 4-buffer mode (a/d tr igger select 4-bu ffer) oper ation .......................................................... ...349 12-8 example of scan mode (a/d trigger scan ) operat ion ......................................................................... ........350 12-9 example of 1-trigger mode (timer trigger select 1-buffer 1-tr igger) oper ation .........................................352 12-10 example of 4-trigger mode (timer trigger select 1-buffer 4-tr igger) oper ation.........................................353 12-11 example of 1-trigger mode (timer trigger select 4-buffer 1-tr igger) oper ation.........................................354 12-12 example of 4-trigger mode (timer trigger select 4-buffer 4-tr igger) oper ation.........................................355 12-13 example of 1-trigger mode (timer trigger scan 1-tr igger) oper ation ....................................................... .356 12-14 example of 4-trigger mode (timer trigger scan 4-tr igger) oper ation ....................................................... .357 12-15 a/d trigger mode a/d conver sion time: when adm1 = 00h .................................................................... .360 12-16 timer trigger mode a/d conversion time: when adm1 = 20h or 30h .......................................................360 12-17 a/d conversion outline: one a/d conversion, fr0 to fr2 bits of adm1 register = 000 (96 clocks).......361 12-18 overa ll erro r ............................................................................................................ .....................................362 12-19 quantizat ion e rror ....................................................................................................... .................................363 12-20 zero-sca le error ......................................................................................................... ..................................363 12-21 full-scal e error......................................................................................................... ....................................364 12-22 differential li nearity error ............................................................................................. ................................364 12-23 integral li nearity error ................................................................................................. .................................365 12-24 sampli ng ti me............................................................................................................ ..................................365 13-1 block diagram of type a................................................................................................... ...........................371 13-2 block diagram of type b................................................................................................... ...........................372 13-3 block diagram of type c................................................................................................... ...........................372 13-4 block diagram of type d................................................................................................... ...........................373 13-5 block diagram of type f ................................................................................................... ...........................373 13-6 block diagram of type g .................................................................................................. ..........................374 13-7 block diagram of type h................................................................................................... ...........................375 13-8 block diagram of type j ................................................................................................... ...........................376 13-9 block diagram of type k................................................................................................... ...........................377 13-10 block diagram of type m .................................................................................................. ...........................378 13-11 block diagram of type n.................................................................................................. ............................379 13-12 block diagram of type o .................................................................................................. ...........................380
user's manual u14980ej2v1ud 22 list of figures (4/4) figure no. title page a-1 100-pin plastic lqfp (fine pitch) (14 14) .................................................................................................446 b-1 example of structure of memory map with error .............................................................................. ............447 b-2 example of structure of memory map prev enting e rror ........................................................................ .......448
user's manual u14980ej2v1ud 23 list of tables table no. title page 3-1 program registers.......................................................................................................... ................................52 3-2 system regi ster nu mbers.................................................................................................... ..........................53 3-3 interrupt/exce ption table .................................................................................................. .............................61 4-1 bus cycles in which wait function is valid ................................................................................. ..................98 4-2 bus prio rity order ......................................................................................................... ................................108 5-1 example of interv al factor settings........................................................................................ ......................149 6-1 relationship between trans fer type and trans fer ob ject ..................................................................... ......188 6-2 external bus cycles during dma transfer.................................................................................... ...............188 6-3 number of minimum exec ution clocks in dma c ycle ............................................................................ ......194 7-1 interrupt/except ion source list............................................................................................ .........................198 7-2 address and bits of in terrupt contro l regi ster ............................................................................. ................212 9-1 clock generator operation using power sa ve control......................................................................... .......239 9-2 operation status in halt mode.............................................................................................. .....................243 9-3 operation after halt mode is released by in terrupt request ................................................................. ...244 9-4 operation status in idle mode .............................................................................................. ......................246 9-5 operation after idle mode is released by inte rrupt re quest ................................................................. ....247 9-6 operation status in software st op mode ..................................................................................... ..............249 9-7 operation after software stop mode is released by inte rrupt req uest ....................................................250 9-8 counting time examples (f xx = 10 f x ) ....................................................................................................... 253 10-1 timer c c onfigurat ion ..................................................................................................... .............................255 10-2 to00 output cont rol ....................................................................................................... .............................271 10-3 timer d c onfigurat ion ..................................................................................................... .............................280 11-1 generated interrupts and default pr ioriti es ............................................................................... ...................300 11-2 reception error c auses .................................................................................................... ...........................309 11-3 baud rate gener ator setting data.......................................................................................... .....................317 11-4 maximum and minimum al lowable baud ra te error ............................................................................. .......319 14-1 operation status of each pin duri ng reset ................................................................................. ................409 14-2 initial value of cpu, internal ram, and on-chip peripheral i/o after reset ..............................................4 11
24 user's manual u14980ej2v1ud chapter 1 introduction the v850e/ma2 is a product of nec electronics? single-c hip microcontroller ?v850 series?. this chapter gives a simple outline of the v850e/ma2. 1.1 outline the v850e/ma2 is a 32-bit single-chip microcontroller that integrates the v850e1 cp u, which is a 32-bit risc- type cpu core for asic, newly developed as the cpu core central to system lsi for the current age of system-on- chip. this device incorporates ram, and various peripheral functions such as memory c ontrollers, a dma controller, real-time pulse unit, serial interfaces, and an a/d converter for realizing high-capacity data processing and sophisticated real-time control. (1) v850e1 cpu the v850e1 cpu is a cpu core that enhances the external bus interf ace performance of the v850 cpu, which is the cpu core integrated in the v850 series , and has added instructions supporting high-level languages, such as c-language s witch statement processing, table lookup branching, stack frame creation/deletion, and data conversion. this enhances the performance of both data processing and control. it is possible to use the software resources of the v850 cpu integrated system since the instruction codes of the v850e1 are upwardly compatible at the obj ect code level with those of the v850 cpu. (2) external memory interface function the v850e/ma2 features various on-chip external memory interfaces including separately configured address (25 bits) and data (16 bits) buses, and sdram and rom interfaces, as well as on-chip memory controllers that can be directly lin ked to page rom, etc., thereby ra ising system perform ance and reducing the number of parts needed for application systems. also, through the dma controller, cpu internal ca lculations and data transfers can be performed simultaneously with transfers to and from the external memory, so it is possible to process large volumes of image data or voice data, etc., and through high-speed exec ution of instructions using internal ram, motor control, communications control and other real time control tasks can be realized simultaneously. (3) a full range of middleware and development environment products the v850e/ma2 can execute middleware such as j peg, jbig, and mh/mr/mmr at high speed. also, middleware that enables voice recognition, voice synthes is, and other such processing is available, and by including these middleware programs, a mu ltimedia system can be easily realized. a development environment system that includes an optimized c compiler, debugger, in-circuit emulator, simulator, system performance analyzer, an d other elements is also available.
chapter 1 introduction 25 user's manual u14980ej2v1ud 1.2 features { number of instructions: 83 { minimum instruction execution time: 25 ns (at internal 40 mhz operation) { general-purpose registers: 32 bits 32 { instruction set: v850e1 cpu signed multiplication (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits): 1 to 2 clocks saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock bit manipulation instructions load/store instructions with long/short format signed load instructions { memory space: 80 mb linear addre ss space (common program/data use) chip select output function: 4 spaces memory block division function: 2, 4, 8 mb/block programmable wait function idle state insertion function { external bus interface: 16-bit data bus (address/data separated) 16-/8-bit bus sizing function bus hold function external wait function address setup wait function endian control function { internal memory: internal ram: 4 kb { interrupts/exceptions: external interrupts: 8 (including nmi) internal interrupts: 23 sources exceptions: 1 source eight levels of priorities can be set. { memory access controller: sdram controller page-rom controller
chapter 1 introduction 26 user's manual u14980ej2v1ud { dma controller: 4 channels transfer units: 8 bits/16 bits maximum transfer count: 65,536 (2 16 ) transfer type: 2-cycle transfer mode: single/single step/block transfer target: memory ? memory, memory ? i/o transfer request: external request/on-chip peripheral i/o/ software dma transfer terminate (terminal count) output signal next address setting function { i/o lines: input ports: 5 i/o ports: 74 { real-time pulse unit: 16-bit timer/event counter: 2 channels 16-bit timers: 2 16-bit capture/compare registers: 4 16-bit interval timer: 4 channels { serial interfaces (sio): asynchronous serial interface (uart) clocked serial interface (csi) csi/uart: 2 channels { a/d converter: 10-bit resolution a/d converter: 4 channels { clock generator: a 10-multiplication function through a pll clock synthesizer. divide-by-two function through an external clock input. { power save function: halt/idle/software stop mode { package: 100-pin plastic lqfp (fine pitch) (14 14) { cmos technology: all static circuits
chapter 1 introduction 27 user's manual u14980ej2v1ud 1.3 applications ink-jet printers, facsimiles, digital still cameras, dvd players, video printers, ppcs, information equipment, etc. 1.4 ordering information part number package inte rnal rom internal ram pd703108gc-8eu 100-pin plastic lqfp (fine pitch) (14 14) none 4 kb pd703108gc-8eu-a 100-pin plastic lqfp (fine pitch) (14 14) none 4 kb remark products with -a at the end of the part number are lead-free products.
chapter 1 introduction 28 user's manual u14980ej2v1ud 1.5 pin configuration (top view) ? 100-pin plastic lqfp (fine pitch) (14 14) pd703108gc-8eu pd703108gc-8eu-a ti000/intp000/p01 dmaak1/pbd1 dmaak0/pbd0 intp011/p12 ti010/intp010/p11 tc0/intp110/p24 nmi/p20 v dd v ss mode1 mode0 reset cksel cv dd x2 x1 cv ss sck1/p45 rxd1/si1/p44 txd1/so1/p43 sck0/p42 rxd0/si0/p41 txd0/so0/p40 av dd /a ref av ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a1/pal1 a0/pal0 d15/pdl15 d14/pdl14 d13/pdl13 d12/pdl12 d11/pdl11 d10/pdl10 d9/pdl9 d8/pdl8 v dd v ss d7/pdl7 d6/pdl6 d5/pdl5 d4/pdl4 d3/pdl3 d2/pdl2 d1/pdl1 d0/pdl0 mode2 dmarq1/intp101/p05 dmarq0/intp100/p04 to00/p03 intp001/p02 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pal2/a2 pal3/a3 pal4/a4 pal5/a5 pal6/a6 pal7/a7 v ss v dd pal8/a8 pal9/a9 pal10/a10 pal11/a11 pal12/a12 pal13/a13 pal14/a14 pal15/a15 v ss v dd pah0/a16 pah1/a17 pah2/a18 pah3/a19 pah4/a20 pah5/a21 pah6/a22 pah7/a23 pah8/a24 pcd0/sdcke pcd1/sdclk pcd2/lbe/sdcas pcd3/ube/sdras pcs0/cs0 pcs3/cs3 pcs4/cs4 pcs7/cs7 pct0/lwr/ldqm pct1/uwr/udqm pct4/rd pct5/we pcm0/wait pcm1/clkout pcm2/hldak pcm3/hldrq pcm4/refrq v ss v dd p70/ani0 p71/ani1 p72/ani2 p73/ani3
chapter 1 introduction 29 user's manual u14980ej2v1ud pin identification a0 to a24: address bus pbd0, pbd1: port bd ani0 to ani3: analog input pcd0 to pcd3: port cd av dd : analog power supply pcm0 to pcm4: port cm av ref : analog reference voltage pcs0, pcs3, : port cs av ss : analog ground pcs4, pcs7 cksel: clock generator operating mode select pct0, pct1, : port ct clkout: clock output pct4, pct5 cs0, cs3, cs4, cs7: chip select pdl0 to pdl15: port dl cv dd : clock generator power supply rd: read strobe cv ss : clock generator ground refrq: refresh request d0 to d15: data bus reset: reset dmaak0, dmaak1: dma acknowledge rxd0, rxd1: receive data dmarq0, dmarq1: dma request sck0, sck1: serial clock hldak: hold acknowledge sdcas: sdram column address strobe hldrq: hold request sdcke: sdram clock enable intp000, intp001, : interrupt request from peripherals sdclk: sdram clock output intp010, intp011, sdras: sdram row address strobe intp100, intp101, si0, si1: serial input intp110 so0, so1: serial output lbe: lower byte enable tc0: terminal count signal ldqm: lower dq mask enable ti000, ti010: timer input lwr: lower write strobe to00: timer output mode0 to mode2: mode txd0, txd1: transmit data nmi: non-maskable interrupt request ube: upper byte enable p01 to p05: port 0 udqm: upper dq mask enable p11, p12: port 1 uwr: upper write strobe p20, p24: port 2 v dd : power supply p40 to p45: port 4 v ss : ground p70 to p73: port 7 wait: wait pah0 to pah8: port ah we: write enable pal0 to pal15: port al x1, x2: crystal
chapter 1 introduction 30 user's manual u14980ej2v1ud 1.6 function block 1.6.1 internal block diagram mode0 to mode2 reset v dd v ss dmarq0, dmarq1 dmaak0, dmaak1 tc0 hldrq hldak cs0, cs3, cs4, cs7 refrq lbe/sdcas ube/sdras sdclk sdcke we rd uwr/udqm lwr/ldqm wait a0 to a24 d0 to d15 nmi intp000, intp001, intp010, intp011 intp100, intp101, intp110 to00 ti000, ti010 intc rpu sio ram 4 kb cpu 32-bit barrel shifter pc system registers general- purpose registers (32 bits 32) alu multiplier (32 32 64) ports pdl0 to pdl15 pal0 to pal15 pah0 to pah8 pcs0, pcs3, pcs4, pcs7 pct0, pct1, pct4, pct5 pcm0 to pcm4 pcd0 to pcd3 pbd0, pbd1 p70 to p73 p40 to p45 p24 p20 p11, p12 p01 to p05 cg system controller bcu clkout cksel x1 x2 cv dd cv ss uart0/csi0 uart1/csi1 adc txd0/so0 rxd0/si0 sck0 txd1/so1 rxd1/si1 sck1 ani0 to ani3 av ref /av dd av ss instruction queue memc sdramc dmac romc prescaler
chapter 1 introduction 31 user's manual u14980ej2v1ud 1.6.2 on-chip units (1) cpu the cpu uses five-stage pipeline control to enable sing le-clock execution of addres s calculations, arithmetic logic operations, data transfers, and almo st all other instruction processing. other dedicated on-chip hardware, su ch as the multiplier (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits) and the barrel shifter (32 bits), help acce lerate processing of complex instructions. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory area and the cpu does not send a bus cycle start request, the bcu generates a prefetch address a nd prefetches the instruction code. the prefetched in struction code is stored in an instruction queue in the cpu. the bcu controls an sdram controller (sdramc), page rom controller (romc), and dma controller (dmac) and performs external memory access and dma transfer. (a) sdram controller (sdramc) the dram controller generates the sdras, sdcas, udqm, and ldqm signals and performs access control for sdram. cas latency 2 and 3 are supported, and the burst length is fixed to 1. a refresh function that supports the cbr refresh cycle and a dynamic self refresh function based on an external input are also available. (b) page rom controller (romc) this controller supports accessing rom that includes the page access function. it performs address comparisons with the immediately preceding bus cycle and executes wait control for normal access (off page)/page access (on page). it can handle page widths of 8 to 128 bytes. (c) dma controller (dmac) instead of the cpu, this controller cont rols data transfer between memory and i/o. there is an address mode, 2-cycle tr ansfer. there are three bus mode s, single transfer, single step transfer, and block transfer. (3) ram ram is mapped from address ffffc000h. during instruction fetch or data access, data c an be accessed from the cpu in 1-clock cycles. (4) interrupt controller (intc) this controller handles hardware interrupt reques ts (nmi, intp0n0, intp0n1, intp10n, intp110) from on- chip peripheral i/o and external hardware (n = 0, 1). ei ght levels of interrupt prio rities can be specified for these interrupt requests, and multiple -interrupt servicing control can be performed for interrupt sources.
chapter 1 introduction 32 user's manual u14980ej2v1ud (5) clock generator (cg) this clock generator supplies frequencies which are 10 times the input clock (f x ) (using an on-chip pll) or 1/2 the input clock (w hen an on-chip pll is not used) as the internal system clock (f xx ). as the input clock, an external oscillator is connected to pins x1 and x2 (only when an on-chip pll synthesizer is used) or an external clock is input from pin x1. (6) real-time pulse unit (rpu) this unit has a 2-channel 16-bit timer/event counter and 4-channel 16-bit interval timer built in, and can measure pulse widths or frequency and output a programmable pulse. (7) serial interfaces (sio) two channels of serial interfaces are provided for which an asynchronous serial interface (uart) and clocked serial interface (csi) modes are selectable. uart transfers data by using the txdn and rxdn pins (n = 0, 1). csi transfers data by using the son, sin, and sckn pins (n = 0, 1). (8) a/d converter (adc) this high-speed, high-resolution 10-bit a/d converter incl udes 4 analog input pins. conversion uses the successive approximation method. (9) ports as shown below, the following ports have general -purpose port functions and control pin functions. port port function control function port 0 5-bit i/o real-time pulse unit i/o, ex ternal interrupt input, dma controller input port 1 2-bit i/o real-time pulse uni t input, external interrupt input port 2 1-bit input, 1-bit i/o nmi input, external interrupt input, dma controller output port 4 6-bit i/o serial interface i/o port 7 4-bit input a/d converter input port al 16-bit i/o external address bus port ah 9-bit i/o external address bus port dl 16-bit i/o external data bus port cs 4-bit i/o external bus interface control signal output port ct 4-bit i/o external bus interface control signal output port cm 5-bit i/o wait insertion signal input, in ternal system clock outpu t, external bus interface control signal i/o port cd 4-bit i/o external bus interface control signal output port bd 2-bit i/o dma controller output
33 user's manual u14980ej2v1ud chapter 2 pin functions the names and functions of the pins in the v850e/ma2 are listed below. these pins can be divided into port pins and non-port pins according to their functions. 2.1 list of pin function (1) port pins (1/2) pin name i/o function alternate function p01 ti000/intp000 p02 intp001 p03 to00 p04 dmarq0/intp100 p05 i/o port 0 5-bit i/o port input/output mode can be specified in 1-bit units. dmarq1/intp101 p11 intp010/ti010 p12 i/o port 1 2-bit i/o port input/output mode can be specified in 1-bit units. intp011 p20 input nmi p24 i/o port 2 p20 is an input-only port. if a valid edge is input, it operates as an nmi input. also, the status of the nmi input is shown by bit 0 of the p2 register. p24 is an i/o port. tc0/intp110 p40 txd0/so0 p41 rxd0/si0 p42 sck0 p43 txd1/so1 p44 rxd1/si1 p45 i/o port 4 6-bit i/o port input/output mode can be specified in 1-bit units. sck1 p70 to p73 input port 7 4-bit input only port ani0 to ani3 pbd0, pbd1 i/o port bd 2-bit i/o port input/output mode can be specified in 1-bit units. dmaak0, dmaak1 pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldrq pcm4 i/o port cm 5-bit i/o port input/output mode can be specified in 1-bit units. refrq
chapter 2 pin functions 34 user's manual u14980ej2v1ud (2/2) pin name i/o function alternate function pct0 lwr/ldqm pct1 uwr/udqm pct4 rd pct5 i/o port ct 4-bit i/o port input/output mode can be specified in 1-bit units. we pcs0 cs0 pcs3 cs3 pcs4 cs4 pcs7 i/o port cs 4-bit i/o port input/output mode can be specified in 1-bit units. cs7 pcd0 sdcke pcd1 sdclk pcd2 lbe/sdcas pcd3 i/o port cd 4-bit i/o port input/output mode can be specified in 1-bit units. ube/sdras pah0 to pah8 i/o port ah 8-/9-bit i/o port input/output mode can be specified in 1-bit units. a16 to a24 pal0 to pal15 i/o port al 8-/16-bit i/o port input/output mode can be specified in 1-bit units. a0 to a15 pdl0 to pdl15 i/o port dl 8-/16-bit i/o port input/output mode can be specified in 1-bit units. d0 to d15
chapter 2 pin functions 35 user's manual u14980ej2v1ud (2) non-port pins (1/2) pin name i/o function alternate function to00 output pulse signal output of timer c0 p03 ti000 p01/intp000 ti010 input external count clock input of timer c0, c1 p11/intp010 intp000 p01/ti000 intp001 external maskable interrupt request input, or timer c0 external capture trigger input p02 intp010 p11/ti010 intp011 input external maskable interrupt request input, or timer c1 external capture trigger input p12 intp100 p04/dmarq0 intp101 p05/dmarq1 intp110 input external maskable interrupt request input p24/tc0 so0 p40/txd0 so1 output csi0, sci1 serial transmission data output (3-wire) p43/txd1 si0 p41/rxd0 si1 input csi0, csi1 serial reception data input (3-wire) p44/rxd1 sck0 p42 sck1 i/o csi0, csi1 serial clock i/o (3-wire) p45 txd0 p40/so0 txd1 output uart0, uart1 serial transmission data output p43/so1 rxd0 p41/si0 rxd1 input uart0, uart1 serial reception data input p44/si1 ani0 to ani3 input analog inputs to the a/d converter p70 to p73 dmarq0 p04/intp100 dmarq1 input dma request signal input p05/intp101 dmaak0 pbd0 dmaak1 output dma acknowledge signal output pbd1 tc0 output dma transfer termination (termina l count) signal output p24/intp110 nmi input non-maskable interrupt request input p20 mode0 to mode2 input v850e/ma2 operating mode specification ? wait input control signal input that inserts a wait in the bus cycle pcm0 hldak output bus hold acknowledge output pcm2 hldrq input bus hold request input pcm3 refrq output refresh request signal output for dram pcm4 lwr output external data lower byte write strobe signal output pct0/ldqm uwr output external data higher byte write strobe signal output pct1/udqm ldqm output output disable/write mask signal output for sdram lower data pct0/lwr udqm output output disable/write mask signal output for sdram higher data pct1/uwr rd output external data bus read strobe signal output pct4 we output write enable signal output for sdram pct5
chapter 2 pin functions 36 user's manual u14980ej2v1ud (2/2) pin name i/o function alternate function cs0 pcs0 cs3 pcs3 cs4 pcs4 cs7 output chip select signal output pcs7 sdcke output sdram clock enable signal output pcd0 sdclk output sdram clock signal output pcd1 sdcas output column address strobe signal output for sdram pcd2/lbe sdras output row address strobe signal output for sdram pcd3/ube lbe output external data bus lower byte enable signal output pcd2/sdcas ube output external data bus higher byte enable signal output pcd3/sdras d0 to d15 i/o 16-bit data bus for external memory pdl0 to pdl15 a0 to a15 pal0 to pal15 a16 to a24 output 25-bit address bus for external memory pah0 to pah8 reset input system reset input ? x1 input ? x2 ? connects the crystal resonator for system clock oscillation. in the case of an external source supplyi ng the clock, it is input to x1. ? clkout output system clock output pcm1 cksel input input which specifies the clock generator's operating mode ? av ref input reference voltage applied to a/d converter av dd av dd ? positive power supply for a/d converter av ref av ss ? ground potential for a/d converter ? cv dd ? positive power supply for t he exclusive clock generator ? cv ss ? ground potential for the exclusive clock generator ? v dd ? positive power supply ? v ss ? ground potential ?
chapter 2 pin functions 37 user's manual u14980ej2v1ud 2.2 pin status the status of each pin after reset, in power-save mo de (software stop, idle, halt modes), and during dma transfer, refresh, and bus hold (th) is shown below. operating status pin reset idle mode/software stop mode halt mode/during dma transfer, refresh bus hold (th) note a0 to a15 (pal0 to pal15) hi-z hi-z operating hi-z a16 to a24 (pah0 to pah8) hi-z hi-z operating hi-z d0 to d15 (pdl0 to pdl15) hi-z hi-z operating hi-z cs0, cs3, cs4, cs7 (pcs0, pcs3, pcs4, pcs7) hi-z h operating hi-z lwr, uwr (pct0, pct1) hi-z h operating hi-z ldqm, udqm (pct0, pct1) ? h operating hi-z rd (pct4) hi-z h operating hi-z we (pct5) hi-z h operating hi-z wait (pcm0) hi-z ? operating ? clkout (pcm1) operati ng l operating operating hldak (pcm2) hi-z h operating l hldrq (pcm3) hi-z ? operating operating refrq (pcm4) hi-z l operating operating sdcke (pcd0) hi-z l operating operating sdclk (pcd1) hi-z l operating operating sdcas (pcd2) ? self operating hi-z lbe (pcd2) hi-z h operating hi-z sdras (pcd3) ? self operating hi-z ube (pcd3) hi-z h operating hi-z dmaak0, dmaak1 (pbd0, pbd1) hi-z h operating h note pins set to the port mode retain their previous state. remark hi-z: high-impedance h: high-level output l: low-level output ? : no sampling of input self: self refresh state when pins are connected to sdram
chapter 2 pin functions 38 user's manual u14980ej2v1ud 2.3 description of pin functions (1) p01 to p05 (port 0) 3-state i/o p01 to p05 constitute a 5-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, t hese pins operate as an inpu t/output for the real-time pulse unit (rpu), external interrupt request inputs, and dma request inputs. the operation mode can be set to port or control mode in 1-bit units, specified by the port 0 mode control register (pmc0). (a) port mode p01 to p05 can be set to input or output in 1- bit units by the port 0 mode register (pm0). (b) control mode p01 to p05 can be set to port/control mode in 1-bit units by the pmc0 register. (i) ti000 (timer input) input this is the external count clock input pin for timer c0. (ii) to00 (timer output) output this pin outputs the pulse signals for timer c0. (iii) intp000, intp001 (interrupt re quest from peri pherals) input these are external interrupt reques t input pins and the external capture trigger input pins for timer c0. (iv) intp100, intp101 (interrupt re quest from peri pherals) input these are external interrupt request input pins. (v) dmarq0, dmarq1 (dma request) input these are dma service request signals. they co rrespond to dma channels 0 and 1, respectively, and operate independently of each other. the prio rity order is fixed to dmarq0 > dmarq1. these signals are sampled at the ri sing edge of the clkout signal. maintain an active level until a dma request is acknowledged.
chapter 2 pin functions 39 user's manual u14980ej2v1ud (2) p11, p12 (port 1) 3-state i/o p11 and p12 constitute a 2-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, t hese pins operate as an input for the real-time pulse unit (rpu) and external interrupt request inputs. the operation mode can be set to port or control mode in 1-bit units, specified by the port 1 mode control register (pmc1). (a) port mode p11 and p12 can be set to input or output in 1- bit units by the port 1 mode register (pm1). (b) control mode p11 and p12 can be set to port/control mode in 1-bit units by the pmc1 register. (i) ti010 (timer input) input this is the external count clock input pin for timer c1. (ii) intp010, intp011 (interrupt re quest from peri pherals) input these are external interrupt reques t input pins and the external capture trigger input pins for timer c1. (3) p20, p24 (port 2) 3-state i/o p20 of port 2 is an input-only port and p24 is an i/o port. besides functioning as an i/o port, in the control mode, p24 operates as ex ternal interrupt request inputs and dma transfer termination outputs (terminal count). t he port/control mode is specified by the port 2 mode control register (pmc2). (a) port mode p24 can be set to input or output by the port 2 mode register (pm2). p20 is an input-only port, and if a valid edge is input, it operates as an nmi input. (b) control mode p24 can be set to port/control mode by the pmc2 register. (i) nmi (non-maskable inte rrupt request) input this is the non-maskable interrupt request input pin. (ii) intp110 (interrupt request from peripherals) input these are external interrupt request input pins. (iii) tc0 (terminal count) output these are signals from the dma controller indicati ng that dma transfer is complete. these signals become active for 1 clock at the rising edge of the clkout signal.
chapter 2 pin functions 40 user's manual u14980ej2v1ud (4) p40 to p45 (port 4) 3-state i/o p40 to p45 constitute a 6-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as in put/outputs for the serial interfaces (uart0/csi0, uart1/csi1). the operation mode can be set to port or control mode in 1-bit units, specified by the port 4 mode control register (pmc4). (a) port mode p40 to p45 can be set to input or output in 1-bi t units by the port 4 mode register (pm4). (b) control mode p40 to p45 can be set to port/control mode in 1-bit units by the pmc4 register. (i) txd0, txd1 (trans mit data) output these pins output uart0, ua rt1 serial transmit data. (ii) rxd0, rxd1 (receive data) input these pins input uart0, ua rt1 serial receive data. (iii) so0, so1 (serial output) output these pins output csi0, csi1 serial transmit data. (iv) si0, si1 (serial input) input these pins input csi0, cs i1 serial receive data. (v) sck0, sck1 (serial clock) 3-state i/o these are the csi0, csi1 serial clock i/o pins. (5) p70 to p73 (port 7) 3-state i/o p70 to p73 constitute a 4-bit input-only port in which all pins are fixed as input pins. besides functioning as a port, in the control mode, these pins operate as analog inputs for the a/d converter. however, the input ports and analog input pins cannot be switched. (a) port mode p70 to p73 are input-only pins. (b) control mode p70 to p73 have alternate functions as pins ani0 to ani3, but these alternate functions are not switchable. (i) ani0 to ani3 (analog input) input these are analog input pins for the a/d converter. connect a capacitor between these pins and av ss to prevent noise-related operation faults. also, do not apply voltage that is outside the range for av ss and av ref to pins that are being used as inputs for the a/d converter. if it is possible for noise above the av ref range or below the av ss to enter, clamp these pins using a diode that has a small v f value.
chapter 2 pin functions 41 user's manual u14980ej2v1ud (6) pbd0, pbd1 (port bd) 3-state i/o pbd0 and pb01 constitute a 2-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as t he dma acknowledge outputs. the operation mode can be set to port or control in 1-bi t units, specified by the port bd mode control register (pmcbd). (a) port mode pbd0 and pbd1 can be set to input or output in 1-bit units by the port bd mode register (pmbd). (b) control mode pbd0 and pbd1 can be set to port/control mode in 1-bit units by the pmcbd register. (i) dmaak0, dmaak1 (dma acknowledge) output these signals show that a dma service request wa s permitted. they correspond to dma channel 0 and 1, respectively, and operate independently of each other. this becomes active only when external memory is being accessed. when dma transfers are being executed between internal ram and internal peripheral i/o, it does not become active. this signal is activated at the rising edge of the clkout signal in the t0, t1r, t1fh state of the dma cycle, and is retained at an ac tive level during dma transfers. (7) pcm0 to pcm4 (port cm) 3-state i/o pcm0 to pcm4 constitute a 5- bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in the control mode, thes e pins operate as the wait insertion signal input, system clock output, bus hold control signal, and refresh request signal output for dram. the operation mode can be set to port or control in 1-bit units, specified by the por t cm mode control register (pmccm). (a) port mode pcm0 to pcm4 can be set to input or output in 1-bit units by the port cm mode register (pmcm). (b) control mode pcm0 to pcm4 can be set to port/control mode in 1-bit units by the pmccm register. (i) wait (wait) input this is the control signal input pin which inserts a data wait in th e bus cycle, and it can be input asynchronously with respect to the clkout signal. when the clkout signal rises, sampling is executed. when the set/hold time is not terminat ed within the sampling timing, wait insertion may not be executed. (ii) clkout (clock output) output this is the internal system clock output pin. (iii) hldak (hold ack nowledge) output in this mode, this pin is the acknowledge signal output pin that indicates high impedance status for the address bus, data bus, and control bus when the v850e/ma2 receives a bus hold request. while this signal is active, the impedance of the address bus, data bus and control bus becomes high and the bus mastership is transferred to the external bus master.
chapter 2 pin functions 42 user's manual u14980ej2v1ud (iv) hldrq (hold request) input in this mode, this pin is the input pin by which an external device requests the v850e/ma2 to release the address bus, data bus, and cont rol bus. this pin accepts asynchronous input for clkout. when this pin is active, the address bus, data bus, a nd control bus are set to high impedance status. this occurs either when the v850e/ma2 completes execution of the current bus cycle or immediately if no bus cycle is being executed, then the hldak sig nal is set as active and the bus is released. in order to make the bus hold state secure, k eep the hldrq signal active until the hldak signal is output. (v) refrq (refresh request) output this is the refresh request signal for dram. in cases where the address is decoded by an external circuit to increase the connected dram, or in cases where external simm?s are connected, this signal is used in ras control during the refresh cycle. this signal becomes active during the refresh cycle. also, during bus hold, it becomes active when a refresh request is generated and informs the exte rnal bus master that a refresh request was generated. (8) pct0, pct1, pc t4, pct5 (port ct) 3-state i/o pct0, pct1, pct4, and pct5 constitute a 4-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in the control mode, t hese pins operate as control signal outputs for when memory is expanded externally. the operation mode can be set to port or control mode in 1-bit units, spec ified by the port ct mode control register (pmcct). (a) port mode pct0, pct1, pct4, and pct5 can be set to input or output in 1-bit units by the port ct mode register (pmct). (b) control mode pct0, pct1, pct4, and pct5 can be set to port/contro l mode in 1-bit units by the pmcct register. (i) lwr (lower byte write strobe) 3-state output this strobe signal shows whether the bus cycle cu rrently being executed is a write cycle for the sram, external rom, or ex ternal peripheral i/o area. for the data bus, the lower byte becomes valid. if the bus cycle is a lower me mory write, it becomes active at the falling edge of the t1 state?s clkout signal and becomes inactive at the falling edge of the t2 state?s clkout signal. (ii) uwr (upper byte write strobe) 3-state output this strobe signal shows whether the bus cycle cu rrently being executed is a write cycle for the sram, external rom, or ex ternal peripheral i/o area. for the data bus, the higher byte becomes valid. if the bus cycle is a higher memory write, it becomes active at the falling edge of the t1 state?s clkout signal and becomes inactive at the falling edge of the t2 st ate?s clkout signal.
chapter 2 pin functions 43 user's manual u14980ej2v1ud (iii) ldqm (lower dq mask enable) 3-state output this is a control signal for the data bus to sdram. for the data bus, the lower byte is valid. this signal carries out sdram output disable contro l during a read operation, and sdram byte mask control during a write operation. (iv) udqm (upper dq mask enable) 3-state output this is a control signal for the data bus to sdram. for the data bus, the higher byte is valid. this signal carries out sdram output disable contro l during a read operation, and sdram byte mask control during a write operation. (v) rd (read strobe) 3-state output this strobe signal shows that the bus cycle current ly being executed is a read cycle for the sram, external rom, external peripheral i/o, or page rom area. in the idle state (ti), it becomes inactive. (vi) we (write enable) 3-state output this signal shows that the bus cycle currently being executed is a write cycle for the sdram area. in the idle state (ti), it becomes inactive. (9) pcs0, pcs3, pcs4, pcs7 (port cs) 3-state i/o pcs0, pcs3, pcs4, and pcs7 constitute a 4-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in the control mode, th ese pins operate as control signal outputs for when memory and peripheral i/o are expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port cs mode control register (pmccs). (a) port mode pcs0, pcs3, pcs4, and pcs7 can be set to input or ou tput in 1-bit units by the port cs mode register (pmcs). (b) control mode pcs0, pcs3, pcs4, and pcs7 can be set to port/control mode in 1-bit units by the pmccs register. (i) cs0, cs3, cs4, cs7 (chip select) 3-state output these are the chip select sig nals for the sram, external rom, external peripheral i/o, and page rom area. the csn signal is assigned to memory block n (n = 0, 3, 4, 7). it becomes active while the bus cycle that accesses the correspondi ng memory block is activated. in the idle state (ti), it becomes inactive. (10) pcd0 to pcd3 (port cd) 3-state i/o pcd0 to pcd3 constitute a 4-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in control mode, these pins operate as control signal outputs for when the memory and peripheral i/o are expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port cd mode control register (pmccd). (a) port mode pcd0 to pcd3 can be set to input or output in 1-bit units using the port cd mode register (pmcd).
chapter 2 pin functions 44 user's manual u14980ej2v1ud (b) control mode pcd0 to pcd3 can be set to port or control mode in 1-bit units using the pmccd register. (i) sdcke (sdram clock enable) 3-state output this is the sdram clock enable output signal. it becomes inactive in self-refresh and standby mode. (ii) sdclk (sdram clock output) 3-state output this is an sdram dedicated clock output signal. the same frequency as the internal system clock is output. (iii) sdcas (sdram column address strobe) 3-state output this is a command output signal for sdram. (iv) sdras (sdram row address strobe) 3-state output this is a command output signal for sdram. (v) lbe (lower byte enable) 3-state output this is the signal that enables the lower byte of the external data bus. (vi) ube (upper byte enable) 3-state output this is the signal that enables the higher byte of the external data bus. (11) pah0 to pah8 (port ah) 3-state i/o pah0 to pah8 constitute an 8- or 9-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in control mode (externa l expansion mode), these pins operate as an address bus (a16 to a24) for when the memory is expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port ah mode control register (pmcah). (a) port mode pah0 to pah8 can be set to input or output in 1-bi t units using the port ah mode register (pmah). (b) control mode pah0 to pah8 can function alternately as a16 to a24 by means of the pmcah register. (i) a16 to a24 (address) 3-state output these are the address output pins of the higher 9 bits of the address bus?s 25-bit address when the external memory is accessed. the output changes in synchronization with the fall of th e clkout signal in the t1 state. in the idle state (t1), the address of the bus cycl e immediately before is retained.
chapter 2 pin functions 45 user's manual u14980ej2v1ud (12) pal0 to pal15 (port al) 3-state i/o pal0 to pal5 constitute an 8- or 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in control mode (externa l expansion mode), these pins operate as an address bus (a0 to a15) for when the memory is expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port al mode control register (pmcal). (a) port mode pal0 to pal15 can be set to input or output in 1-bi t units using the port al mode register (pmal). (b) control mode pal0 to pal15 can function alternately as a0 to a15 by means of the pmcal register. (i) a0 to a15 (address) 3-state output these are the address output pins of the lower 16 bits of the addr ess bus?s 25-bit address when the external memory is accessed. the output changes in synchronization with the fall of th e clkout signal in the t1 state. in the idle state (t1), the address of the bus cycl e immediately before is retained. (13) pdl0 to pdl15 (port dl) 3-state i/o pdl0 to pdl15 constitute an 8- or 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in control mode (exter nal expansion mode), these pins operate as a data bus (d0 to d15) for when the memory is expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port dl mode control register (pmcdl). (a) port mode pdl0 to pdl15 can be set to input or output in 1-bi t units using the port dl mode register (pmdl). (b) control mode pdl0 to pdl15 can function alternately as d0 to d15 by means of the pmcdl register. (i) d0 to d15 (data) 3-state i/o these pins constitute a data bus for when the exte rnal memory is accessed. these are 16-bit data i/o bus pins. the output changes in synchronization with the rise of the clkout signal in the t1 state. in the idle state (t1), these pi ns become high impedance. (14) cksel (clock generator op erating mode select) input this is an input pin which specifies the clock generator?s operating mode. (15) mode0 to mode2 (mode) input these are input pins which specify the operating mode.
chapter 2 pin functions 46 user's manual u14980ej2v1ud (16) reset (reset) input reset input is asynchronous input for a signal that has a constant low level width regardless of the operating clock?s status. when this signal is input, a system reset is executed as the first priority ahead of all other operations. in addition to being used for ordinary initialization/star t operations, this pin can also be used to release a standby mode (halt, idle, or software stop). (17) x1, x2 (crystal) these pins are used to connect the res onator that generates the system clock. (18) cv dd (power supply for clock generator) this pin supplies positive power to the clock generator. (19) cv ss (ground for clock generator) this is the ground pin for the clock generator. (20) v dd (power supply) these are the positive power supply pins for each internal unit. all the v dd pins should be connected to a positive power source. (21) v ss (ground) these are ground pins. all the v ss pins should be connected to ground. (22) av dd (analog power supply) this is the analog positive power su pply pin for the a/d converter. (23) av ss (analog ground) this is the ground pin for the a/d converter. (24) av ref (analog reference voltage) input this is the reference voltage supply pin for the a/d converter.
chapter 2 pin functions 47 user's manual u14980ej2v1ud 2.4 pin i/o circuits and recommende d connection of unused pins it is recommended that 1 to 10 k ? resistors be used when connecting to v dd or v ss via resistors. (1/2) pin name i/o circuit type recommended connection p01/intp000/ti000 p02/intp001 5-ac p03/to00 5 p04/dmarq0/intp100, p05/dmarq1/intp101 p11/intp010/ti010, p12/intp011 5-ac input: independently connect to v dd or v ss via a resistor output: leave open p20/nmi 2 connect to v ss directly. p24/tc0/intp110 5-ac p40/txd0/so0 5 p41/rxd0/si0 p42/sck0 5-ac p43/txd1/so1 5 p44/rxd1/si1 p45/sck1 5-ac input: independently connect to v dd or v ss via a resistor output: leave open p70/ani0 to p73/ani3 9 connect to v ss directly. pbd0/dmaak0, pbd1/dmaak1 5 input: independently connect to v dd or v ss via a resistor output: leave open pcm0/wait 5 input: independently connect to v dd via a resistor pcm1/clkout pcm2/hldak 5 input: independently connect to v dd or v ss via a resistor output: leave open pcm3/hldrq 5 input: independently connect to v dd via a resistor pcm4/refrq pct0/lwr/ldqm pct1/uwr/udqm pct4/rd pct5/we pcs0/cs0 pcs3/cs3 pcs4/cs4 pcs7/cs7 5 input: independently connect to v dd or v ss via a resistor output: leave open
chapter 2 pin functions 48 user's manual u14980ej2v1ud (2/2) pin name i/o circuit type recommended connection pcd0/sdcke pcd1/sdclk pcd2/lbe/sdcas pcd3/ube/sdras pah0/a16 to pah8/a24 pal0/a0 to pal15/a15 pdl0/d0 to pdl15/d15 5 input: independently connect to v dd or v ss via a resistor output: leave open mode0 to mode2 ? reset 2 ? cksel 1 ? av ss ? connect to v ss . av dd /av ref ? connect to v dd .
chapter 2 pin functions 49 user's manual u14980ej2v1ud 2.5 pin i/o circuits type 1 type 2 type 5 p-ch n-ch in v dd in schmitt-triggered input with hysteresis characteristics p-ch n-ch v dd in/out data output disable input enable type 5-ac p-ch n-ch v dd in/out data output disable input enable in comparator + v ref (threshold voltage) p-ch n-ch input enable type 9
50 user's manual u14980ej2v1ud chapter 3 cpu function the cpu of the v850e/ma2 is based on risc architecture and executes almost all the instructions in one clock cycle, using 5-stage pipeline control. 3.1 features ? minimum instruction cycle: 25 ns (at internal 40 mhz operation) memory space program space: 8 mb linear data space: 4 gb thirty-two 32-bit general-purpose registers internal 32-bit architecture five-stage pipeline control multiplication/division instructions saturated operation instructions one-clock 32-bit shift instruction load/store instructions with long/short format four types of bit manipulation instructions set1 clr1 not1 tst1
chapter 3 cpu function 51 user's manual u14980ej2v1ud 3.2 cpu register set the registers of the v850e/ma2 can be classified into tw o categories: a general-purpose program register set and a dedicated system register set. all the registers are 32-bit width. for details, refer to the v850e1 architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrrupt source register) fepc fepsw (status saving register during nmi) (status saving register during nmi) eipc eipsw (status saving register during interrupt) (status saving register during interrupt) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (status saving register during exception/debug trap) (status saving register during exception/debug trap) ctpc ctpsw (status saving register during callt execution) (status saving register during callt execution)
chapter 3 cpu function 52 user's manual u14980ej2v1ud 3.2.1 program register set the program register set includes general -purpose registers and a program counter. (1) general-purpose registers thirty-two general-purpose registers, r0 to r31, are av ailable. any of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instruct ions, and care must be exercised when using these registers. r0 is a register that always holds 0, and is used for operations using 0 and offset 0 addressing. r30 is used, by means of the sld and sst instructions, as a base pointer for when memory is accessed. also, r1, r3 to r5, and r31 are implicitly used by the as sembler and c compiler. ther efore, before using these registers, their contents must be save d so that they are not lost. th e contents must be restored to the registers after the registers have been used. r2 may be used by the real-time os. if the real-time os does not use r2, it can be used as a variable register. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register working register for genera ting 32-bit immediate data r2 address/data variable register (when r2 is not used by the real-time os) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area (where program code is located) r6 to r29 address/dat a variable registers r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution remark for detailed descriptions of r1, r3 to r5, and r31, which are used by the assembler and c compiler, refer to the ca850 (c compiler package) asse mbly language user's manual . (2) program counter (pc) this register holds the instruction address during program execution. the lower 26 bi ts of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occurs from bit 25 to 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address during execution 0 after reset 00000000h
chapter 3 cpu function 53 user's manual u14980ej2v1ud 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. to read/write these system r egisters, specify a system register number indicated below using the system register load/store instruction (lds r or stsr instruction). table 3-2. system register numbers operand specification no. system register name ldsr instruction stsr instruction 0 status saving register during interrupt (eipc) note 1 { { 1 status saving register during interrupt (eipsw) { { 2 status saving register during nmi (fepc) { { 3 status saving register during nmi (fepsw) { { 4 interrupt source register (ecr) { 5 program status word (psw) { { 6 to 15 reserved number for future function expansion (operations that access these register numbers cannot be guaranteed). 16 status saving register du ring callt execution (ctpc) { { 17 status saving register du ring callt execution (ctpsw) { { 18 status saving register du ring exception/debug trap (dbpc) { note 2 { 19 status saving register during exception/debug trap (dbpsw) { note 2 { 20 callt base pointer (ctbp) { { 21 to 31 reserved number for future function expansion (operations that access these register numbers cannot be guaranteed). notes 1. because this register has only one set, to enable multip le interrupts, it is necessary to save this register by program. 2. access is only possible while the dbtrap instruction is executed. caution even if bit 0 of eipc, fepc, or ctpc is set to 1 with the ldsr instruction, bit 0 will be ignored when the program returned by th e reti instruction after interrupt servicing (because bit 0 of the pc is fixed to 0). when setting the value of ei pc, fepc, or ctpc, use the even value (bit 0 = 0). remark { : access allowed : access prohibited (1) interrupt source register (ecr) 31 0 ecr fecc eicc after reset 00000000h 16 15 bit position bit name function 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception/maskable interrupt
chapter 3 cpu function 54 user's manual u14980ej2v1ud (2) program status word (psw) 31 0 psw rfu after reset 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag function 31 to 8 rfu reserved field (fixed to 0). 7 np indicates that non-maskable interrupt (nmi ) servicing is in prog ress. this flag is set when an nmi is acknowledged, and disables multiple interrupts. 0: nmi servicing not under execution. 1: nmi servicing under execution. 6 ep indicates that exception processing is in progress. this flag is set when an exception is generated. moreover, interrupt requests can be acknowledged when this bit is set. 0: exception processing not under execution. 1: exception processing under execution. 5 id displays whether a maskable interr upt request can be acknowledged or not. 0: interrupt enabled. 1: interrupt disabled. 4 sat note displays that the operation result of a saturated operation processing instruction is saturated due to overflow. because this is a the cumulative flag, if the operation result is saturated by the satura tion operation instruction, this bit is set (1), but is not cleared (0) even if the oper ation results of subsequent instructions are not saturated. to clear (0) this bit, load the data in psw. note that in a general arithmetic operation, this bit is neither set (1) nor cleared (0). 0: not saturated. 1: saturated. 3 cy this flag is set if carry or borrow occu rs as result of operation (if carry or borrow does not occur, it is reset). 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note this flag is set if overfl ow occurs during operation (if overflow does not occur, it is reset). 0: overflow does not occur. 1: overflow occurs. 1 s note this flag is set if the result of operati on is negative (it is reset if the result is positive). 0: the operation result was positive or 0. 1: the operation result was negative. 0 z this flag is set if the result of operation is zero (if the result is not zero, it is reset). 0: the operation result was not 0. 1: the operation result was 0. note the result of a saturation-processed operation is dete rmined by the contents of the ov and s flags in the saturation operation. simply setting the ov flag (1 ) will set the sat flag (1) in a saturation operation. flag status status of operation result sat ov s saturation-processed operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (not exceeding the maximum) 0 negative (not exceeding the maximum) retain the value before operation 0 1 operation result itself
chapter 3 cpu function 55 user's manual u14980ej2v1ud 3.3 operation modes 3.3.1 operation modes the v850e/ma2 has the following oper ation modes. mode specification is carried out by the mode0 to mode2 pins. (1) romless modes 0, 1 after system reset is cleared, each pin related to the bus interface enters th e control mode, program execution branches to the external device?s (memory) reset entry address, and instruction processing starts. in romless mode 0, the data bus is a 16-bit data bus an d in romless mode 1, the data bus is an 8-bit data bus. 3.3.2 operation mode specification the operation mode is specified accord ing to the status of t he mode0 to mode2 pins. in an application system fix the specification of these pins and do not change them durin g operation. operation is not guaranteed if these pins are changed during operation. mode2 mode1 mode0 oper ation mode remarks l l l romless mode 0 16-bit data bus l l h normal operation mode romless mode 1 8-bit data bus other than above setting prohibited remarks l: low-level input h: high-level input
chapter 3 cpu function 56 user's manual u14980ej2v1ud 3.4 address space 3.4.1 cpu address space the cpu of the v850e/ma2 is of 32-bi t architecture and supports up to 4 gb of address space (data space) during operand addressing (data access). also, in instruction addr ess addressing, a maximum of 8 mb of linear address space (program space) is supported. the following shows the cpu address space. figure 3-1. cpu address space ffffffffh 00800000h 007fffffh 00000000h data area (4 gb note ) program area (8 mb linear) cpu address space note however, use of a 2.75 gb area is prohibited.
chapter 3 cpu function 57 user's manual u14980ej2v1ud 3.4.2 image a 256 mb physical address space is seen as 16 images in the 4 gb cpu address space. in actuality, the same 256 mb physical address space is accessed regardless of the va lues of bits 31 to 28 of the cpu address. figure 3-2 shows the image of the virtual addressing space. physical address x0000000h can be seen as cpu address 00000000h, and in addition, can be seen as address 10000000h, address 20000000h, ? , address e0000000h, or address f0000000h. caution of the 256 mb physical addr ess space of the v850e/ma2, only an 80 mb area is usable (see 4.3 memory block function). therefore, the space th at can be addressed in the operand addressing mode is not 4 gb but 1.25 gb. figure 3-2. images on address space ffffffffh f0000000h efffffffh 00000000h image image image internal ram peripheral i/o external memory physical address space fffffffh 0000000h image image e0000000h dfffffffh 20000000h 1fffffffh 10000000h 0fffffffh cpu address space
chapter 3 cpu function 58 user's manual u14980ej2v1ud 3.4.3 wrap-around of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are set to ?0?, and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calculation, the higher 6 bits ignore the carry or borrow. therefore, the lower-limit address of the program sp ace, address 00000000h, and the upper-limit address 03ffffffh become contiguous addresses. wrap-around refers to a sit uation like this w hereby the lower- limit address and upper-limit address become contiguous. caution the 4 kb area of 03fff000h to 03ffffffh can be seen as an image of 0ffff000h to 0fffffffh. this area is access- prohibited. therefo re, do not execute any branch address calculation in which the result will r eside in any part of this area. 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction ( ) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit address of the program sp ace, address 00000000h, and the upper-limit address ffffffffh are contiguous addresses, and the data space is wrapped around at th e boundary of these addresses. fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction ( ) direction
chapter 3 cpu function 59 user's manual u14980ej2v1ud 3.4.4 memory map the v850e/ma2 reserves areas as shown below. figure 3-3. memory map xfffffffh internal peripheral i/o area undefined internal ram area external memory area 256 mb 4 kb xffff000h xfffefffh x0000000h xfffd000h xfffcfffh xfffc000h xfffbfffh 4 kb
chapter 3 cpu function 60 user's manual u14980ej2v1ud 3.4.5 area (1) memory area an 80 mb external memory area is available for memo ry area. the lower 8 mb can be used as program/data area and the higher 72 mb as data area. the addres ses of the external memory area are as follows. x0000000h to x07fffffh, x4000000h to x5ffffffh, x8000000h to x9ffffffh, xf800000h to xfffbfffh access to the memory area uses the chip select signal assigned to each memory block (which is carried out in the cs unit set by chip area selectio n control registers 0 and 1 (csc0, csc1)). note that the internal ram and in ternal peripheral i/o areas cannot be ac cessed as external memory areas. (a) interrupt/exception table the v850e/ma2 increases the interrupt response s peed by assigning handler addresses corresponding to interrupts/exceptions. the collection of these handler addresses is called an interrupt /exception table. when an interrupt/exception request is acknowledged, executio n jumps to the handler address, and the program written at that memory is exec uted. table 3-3 shows the source s of interrupts/exceptions, and the corresponding addresses. remark in order to restore correct operation after rese t, provide a handler address to the reset routine in address 0 of the external memory.
chapter 3 cpu function 61 user's manual u14980ej2v1ud table 3-3. interrupt/exception table start address of interrupt/exception table interrupt/exception source 00000000h reset 00000010h nmi 00000040h trap0n (n = 0 to f) 00000050h trap1n (n = 0 to f) 00000060h ilgop/dbg0 00000080h intov00 00000090h intov01 000000c0h intp000/intm000 000000d0h intp001/intm001 000000e0h intp010/intm010 000000f0h intp011/intm011 00000140h intp100 00000150h intp101 00000180h intp110 00000240h intcmd0 00000250h intcmd1 00000260h intcmd2 00000270h intcmd3 00000280h intdma0 00000290h intdma1 000002a0h intdma2 000002b0h intdma3 000002c0h intcsi0 000002d0h intser0 000002e0h intsr0 000002f0h intst0 00000300h intcsi1 00000310h intser1 00000320h intsr1 00000330h intst1 00000380h intad
chapter 3 cpu function 62 user's manual u14980ej2v1ud (2) internal ram area the 12 kb of addresses fffc000h to fffefffh are reserved for the internal ram area. the 12 kb area of 3ffc000h to 3ffefffh can be seen as an image of fffc000h to fffefffh. the 4 kb of addresses fffc000h to fffcfffh ar e provided as physical internal ram. caution addresses fffd000h to fffefffh are access-prohibited. internal ram area (4 kb) access prohibited fffefffh fffd000h fffcfffh fffc000h
chapter 3 cpu function 63 user's manual u14980ej2v1ud (3) internal peripheral i/o area 4 kb of memory, addresses ffff000h to fffffffh, ar e provided as an internal peripheral i/o area. 3fff000h to 3ffffffh note can be seen as an image of ffff000h to fffffffh. note addresses 3fff000h to 3ffffffh are access-proh ibited. to access the internal peripheral i/o, specify addresses ffff000h to fffffffh. fffffffh ffff000h internal peripheral i/o area (4 kb) peripheral i/o registers associated with the operation mode spec ification and the state monitoring for the internal peripherals i/o are all memo ry-mapped to the internal peripheral i/o area. program fetches cannot be executed from this area. cautions 1. in the v850e/ma2, no registers exist whic h are capable of word access, but if a register is word accessed, halfword access is performe d twice in the order of lower address, then higher address of the word area, disr egarding the lower 2 bits of the address. 2. for registers in which byte access is possible, if halfword access is executed, the higher 8 bits become undefined during the read operation, and the lower 8 bits of data are written to the register during the write operation. 3. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. addresses 3fff000h to 3ffffffh cannot be specified as the source/destination address of dma transfer. be sure to use addresses ffff000h to fffffffh for the source/destination address of dma transfer.
chapter 3 cpu function 64 user's manual u14980ej2v1ud 3.4.6 external memory expansion by setting the port n mode control register (pmcn) to c ontrol mode, an external memory device can be connected to the external memory space using each pin of ports al , ah, dl, cs, ct, cm, and cd. each register is set by selecting control mode for each pin of these por ts using pmcn (n = al, ah, dl, cs, ct, cm, cd). note that the status after reset differs as shown below in accordance with the operating mode specification set by the mode0 to mode2 pins (refer to 3.3 operation modes concerning the operation modes). (a) in the case of romless mode 0 because each pin of ports al, ah, dl, cs, ct, cm, and cd enters control mode following a reset, external memory can be used without making changes to the port n mode control register (pmcn) (the external data bus width is 16 bits). (b) in the case of romless mode 1 because each pin of ports al, ah, dl, cs, ct, cm, and cd enters control mode following a reset, external memory can be used without making changes to the port n mode control register (pmcn) (the external data bus width is 8 bits). remark n = al, ah, dl, cs, ct, cm, cd
chapter 3 cpu function 65 user's manual u14980ej2v1ud 3.4.7 recommended use of address space the architecture of the v850e/ma2 r equires that a register that serves as a pointer be secured for address generation when performing operand data access in the data space. operand data access from an instruction can be directly executed at the address in this pointer register 32 kb. however, because there is a limit to which general- purpose registers are used as a pointer register, by mini mizing the deterioration of address calculation performance when changing the pointer value, the nu mber of usable general-purpose registers for handling variables is maximized, and the program size can be saved. (1) program space of the 32 bits of the program counter (pc), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. of those valid bits, a contiguous 8 mb space, starting from address 00000000h, corresponds to the memory map of the program space. (2) data space with the v850e/ma2, a 256 mb physi cal address space is seen as 16 images in the 4 gb cpu address space. the highest bit (bit 25) of this 26-bit address is assigned as an address sign-extended to 32 bits. of the 256 mb physical address space, only an 80 mb area is usable. therefore, the space that can be addressed in the operand addressing mode is not 4 gb but 1.25 gb. example application of wrap-around 00007fffh (r=) 00000000h ffffd000h ffff8000h external/memory area internal peripheral i/o area external/memory area fffff000h ffffefffh ffffbfffh ffffcfffh ffffc000h internal ram area 32 kb 4 kb 4 kb 16 kb 0001ffffh when r = r0 (zero register) is specified with the ld /st disp16 [r] instruction, an addressing range of 00000000h 32 kb can be referenced with the sign-extended disp 16. by mapping the external memory area in the 16 kb area in the figure, all resources including internal hardware can be accessed with one pointer. the zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers for the pointer.
chapter 3 cpu function 66 user's manual u14980ej2v1ud 3.4.8 peripheral i/o registers (1/6) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff000h port al pal r/w { undefined fffff000h port all pall r/w { { undefined fffff001h port alh palh r/w { { undefined fffff002h port ah pah r/w { undefined fffff002h port ahl pahl r/w { { undefined fffff003h port ahh pahh r/w { { undefined fffff004h port dl pdl r/w { undefined fffff004h port dll pdll r/w { { undefined fffff005h port dlh pdlh r/w { { undefined fffff008h port cs pcs r/w { { undefined fffff00ah port ct pct r/w { { undefined fffff00ch port cm pcm r/w { { undefined fffff00eh port cd pcd r/w { { undefined fffff012h port bd pbd r/w { { undefined fffff020h port al mode register pmal r/w { ffffh fffff020h port al mode register l pmall r/w { { ffh fffff021h port al mode register h pmalh r/w { { ffh fffff022h port ah mode register pmah r/w { ffffh fffff022h port ah mode register l pmahl r/w { { ffh fffff023h port ah mode register h pmahh r/w { { ffh fffff024h port dl mode register pmdl r/w { ffffh fffff024h port dl mode register l pmdll r/w { { ffh fffff025h port dl mode register h pmdlh r/w { { ffh fffff028h port cs mode register pmcs r/w { { ffh fffff02ah port ct mode register pmct r/w { { ffh fffff02ch port cm mode register pmcm r/w { { ffh fffff02eh port cd mode register pmcd r/w { { ffh fffff032h port bd mode register pmbd r/w { { ffh fffff040h port al mode control register pmcal r/w { ffffh fffff040h port al mode control register l pmcall r/w { { ffh fffff041h port al mode control register h pmcalh r/w { { ffh fffff042h port ah mode control register pmcah r/w { 01ffh fffff042h port ah mode control register l pmcahl r/w { { ffh fffff043h port ah mode control register h pmcahh r/w { { 01h
chapter 3 cpu function 67 user's manual u14980ej2v1ud (2/6) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff044h port dl mode control register pmcdl r/w { ffffh fffff044h port dl mode control register l pmcdll r/w { { ffh fffff045h port dl mode control register h pmcdlh r/w { { ffh fffff048h port cs mode control register pmccs r/w { { 99h fffff04ah port ct mode control register pmcct r/w { { 33h fffff04ch port cm mode control register pmccm r/w { { 1fh fffff04eh port cd mode control register pmccd r/w { { 0fh fffff04fh port cd function control register pfccd r/w { { 00h fffff052h port bd mode control register pmcbd r/w { { 00h fffff060h chip area select control register 0 csc0 r/w { 2c11h fffff062h chip area select control register 1 csc1 r/w { 2c11h fffff066h bus size cofiguration register bsc r/w { 0000h/5555h fffff068h endian configuration register bec r/w { 0000h fffff06eh system wait control register vswc r/w { 77h fffff080h dma source address register 0l dsa0l r/w { undefined fffff082h dma source address register 0h dsa0h r/w { undefined fffff084h dma destination address register 0l dda0l r/w { undefined fffff086h dma destination address register 0h dda0h r/w { undefined fffff088h dma source address register 1l dsa1l r/w { undefined fffff08ah dma source address register 1h dsa1h r/w { undefined fffff08ch dma destination address register 1l dda1l r/w { undefined fffff08eh dma destination address register 1h dda1h r/w { undefined fffff090h dma source address register 2l dsa2l r/w { undefined fffff092h dma source address register 2h dsa2h r/w { undefined fffff094h dma destination address register 2l dda2l r/w { undefined fffff096h dma destination address register 2h dda2h r/w { undefined fffff098h dma source address register 3l dsa3l r/w { undefined fffff09ah dma source address register 3h dsa3h r/w { undefined fffff09ch dma destination address register 3l dda3l r/w { undefined fffff09eh dma destination address register 3h dda3h r/w { undefined fffff0c0h dma byte count register 0 dbc0 r/w { undefined fffff0c2h dma byte count register 1 dbc1 r/w { undefined fffff0c4h dma byte count register 2 dbc2 r/w { undefined fffff0c6h dma byte count register 3 dbc3 r/w { undefined fffff0d0h dma addressing control register 0 dadc0 r/w { 0000h fffff0d2h dma addressing control register 1 dadc1 r/w { 0000h fffff0d4h dma addressing control register 2 dadc2 r/w { 0000h
chapter 3 cpu function 68 user's manual u14980ej2v1ud (3/6) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff0d6h dma addressing control register 3 dadc3 r/w { 0000h fffff0e0h dma channel control register 0 dchc0 r/w { { 00h fffff0e2h dma channel control register 1 dchc1 r/w { { 00h fffff0e4h dma channel control register 2 dchc2 r/w { { 00h fffff0e6h dma channel control register 3 dchc3 r/w { { 00h fffff0f0h dma disable status register ddis r { 00h fffff0f2h dma restart register drst r/w { 00h fffff100h interrupt mask register 0 imr0 r/w { ffffh fffff100h interrupt mask register 0l imr0l r/w { { ffh fffff101h interrupt mask register 0h imr0h r/w { { ffh fffff102h interrupt mask register 1 imr1 r/w { ffffh fffff102h interrupt mask register 1l imr1l r/w { { ffh fffff103h interrupt mask register 1h imr1h r/w { { ffh fffff104h interrupt mask register 2 imr2 r/w { ffffh fffff104h interrupt mask register 2l imr2l r/w { { ffh fffff105h interrupt mask register 2h imr2h r/w { { ffh fffff106h interrupt mask register 3 imr3 r/w { ffffh fffff106h interrupt mask register 3l imr3l r/w { { ffh fffff107h interrupt mask register 3h imr3h r/w { { ffh fffff110h interrupt control register ovic00 r/w { { 47h fffff112h interrupt control register ovic01 r/w { { 47h fffff118h interrupt control register p00ic0 r/w { { 47h fffff11ah interrupt control register p00ic1 r/w { { 47h fffff11ch interrupt control register p01ic0 r/w { { 47h fffff11eh interrupt control register p01ic1 r/w { { 47h fffff128h interrupt control register p10ic0 r/w { { 47h fffff12ah interrupt control register p10ic1 r/w { { 47h fffff130h interrupt control register p11ic0 r/w { { 47h fffff148h interrupt control register cmicd0 r/w { { 47h fffff14ah interrupt control register cmicd1 r/w { { 47h fffff14ch interrupt control register cmicd2 r/w { { 47h fffff14eh interrupt control register cmicd3 r/w { { 47h fffff150h interrupt control register dmaic0 r/w { { 47h fffff152h interrupt control register dmaic1 r/w { { 47h fffff154h interrupt control register dmaic2 r/w { { 47h fffff156h interrupt control register dmaic3 r/w { { 47h fffff158h interrupt control register csiic0 r/w { { 47h
chapter 3 cpu function 69 user's manual u14980ej2v1ud (4/6) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff15ah interrupt control register seic0 r/w { { 47h fffff15ch interrupt control register sric0 r/w { { 47h fffff15eh interrupt control register stic0 r/w { { 47h fffff160h interrupt control register csiic1 r/w { { 47h fffff162h interrupt control register seic1 r/w { { 47h fffff164h interrupt control register sric1 r/w { { 47h fffff166h interrupt control register stic1 r/w { { 47h fffff170h interrupt control register adic r/w { { 47h fffff1fah in-service priority register ispr r { { 00h fffff1fch command register prcmd w { undefined fffff1feh power save control register psc r/w { { 00h fffff200h a/d converter mode register 0 adm0 r/w { { 00h fffff201h a/d converter mode register 1 adm1 r/w { 07h fffff202h a/d converter mode register 2 adm2 r/w { { 00h fffff210h a/d conversion result register 0 (10 bits) adcr0 r { 0000h fffff212h a/d conversion result register 1 (10 bits) adcr1 r { 0000h fffff214h a/d conversion result register 2 (10 bits) adcr2 r { 0000h fffff216h a/d conversion result register 3 (10 bits) adcr3 r { 0000h fffff220h a/d conversion result register 0h (8 bits) adcr0h r { 00h fffff221h a/d conversion result register 1h (8 bits) adcr1h r { 00h fffff222h a/d conversion result register 2h (8 bits) adcr2h r { 00h fffff223h a/d conversion result register 3h (8 bits) adcr3h r { 00h fffff400h port 0 p0 r/w { { undefined fffff402h port 1 p1 r/w { { undefined fffff404h port 2 p2 r/w { { undefined fffff408h port 4 p4 r/w { { undefined fffff40eh port 7 p7 r/w { { undefined fffff420h port 0 mode register pm0 r/w { { ffh fffff422h port 1 mode register pm1 r/w { { ffh fffff424h port 2 mode register pm2 r/w { { ffh fffff428h port 4 mode register pm4 r/w { { ffh fffff440h port 0 mode control register pmc0 r/w { { 00h fffff442h port 1 mode control register pmc1 r/w { { 00h fffff444h port 2 mode control register pmc2 r/w { { 01h fffff448h port 4 mode control register pmc4 r/w { { 00h fffff460h port 0 function control register pfc0 r/w { { 00h fffff464h port 2 function control register pfc2 r/w { { 00h
chapter 3 cpu function 70 user's manual u14980ej2v1ud (5/6) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff468h port 4 function control register pfc4 r/w { { 00h fffff480h bus cycle type configuration register 0 bct0 r/w { 8888h fffff482h bus cycle type configuration register 1 bct1 r/w { 8888h fffff484h data wait control register 0 dwc0 r/w { 7777h fffff486h data wait control register 1 dwc1 r/w { 7777h fffff488h bus cycle control register bcc r/w { ffffh fffff48ah address setup wait control register asc r/w { ffffh fffff49ah page-rom configurat ion register prc r/w { 7000h fffff4ach sdram configuration register 3 scr3 r/w { 0000h fffff4aeh sdram refresh control register 3 rfs3 r/w { 0000h fffff4b0h sdram configuration register 4 scr4 r/w { 0000h fffff4b2h sdram refresh control register 4 rfs4 r/w { 0000h fffff540h timer d0 tmd0 r { 0000h fffff542h compare register d0 cmd0 r/w { 0000h fffff544h timer mode control register d0 tmcd0 r/w { { 00h fffff550h timer d1 tmd1 r { 0000h fffff552h compare register d1 cmd1 r/w { 0000h fffff554h timer mode control register d1 tmcd1 r/w { { 00h fffff560h timer d2 tmd2 r { 0000h fffff562h compare register d2 cmd2 r/w { 0000h fffff564h timer mode control register d2 tmcd2 r/w { { 00h fffff570h timer d3 tmd3 r { 0000h fffff572h compare register d3 cmd3 r/w { 0000h fffff574h timer mode control register d3 tmcd3 r/w { { 00h fffff600h timer c0 tmc0 r { 0000h fffff602h capture/compare register c00 ccc00 r/w { 0000h fffff604h capture/compare register c01 ccc01 r/w { 0000h fffff606h timer mode control register c00 tmcc00 r/w { { 00h fffff608h timer mode control register c01 tmcc01 r/w { 20h fffff609h valid edge select register c0 sesc0 r/w { 00h fffff610h timer c1 tmc1 r { 0000h fffff612h capture/compare register c10 ccc10 r/w { 0000h fffff614h capture/compare register c11 ccc11 r/w { 0000h fffff616h timer mode control register c10 tmcc10 r/w { { 00h fffff618h timer mode control register c11 tmcc11 r/w { 20h fffff619h valid edge select register c1 sesc1 r/w { 00h fffff800h peripheral command register phcmd w { undefined
chapter 3 cpu function 71 user's manual u14980ej2v1ud (6/6) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff802h peripheral status register phs r/w { { 00h fffff810h dma trigger factor register 0 dtfr0 r/w { { 00h fffff812h dma trigger factor register 1 dtfr1 r/w { { 00h fffff814h dma trigger factor register 2 dtfr2 r/w { { 00h fffff816h dma trigger factor register 3 dtfr3 r/w { { 00h fffff820h power save mode register psmr r/w { { 00h fffff822h clock control register ckc r/w { 00h fffff824h lock register lockr r { { 0xh fffff880h external interrupt mode register 0 intm0 r/w { { 00h fffff882h external interrupt mode register 1 intm1 r/w { 00h fffff884h external interrupt mode register 2 intm2 r/w { 00h fffff8a0h dma terminal count output control register dtoc r/w { { 01h fffff900h clocked serial in terface mode register 0 csim0 r/w { { 00h fffff901h clocked serial interf ace clock select register 0 csic0 r/w { 00h fffff902h serial i/o shift register 0 sio0 r { 00h fffff903h receive-only serial i/o shift register 0 sioe0 r { 00h fffff904h clocked serial interfac e transmit buffer register 0 sotb0 r/w { 00h fffff910h clocked serial in terface mode register 1 csim1 r/w { { 00h fffff911h clocked serial interf ace clock select register 1 csic1 r/w { 00h fffff912h serial i/o shift register 1 sio1 r { 00h fffff913h receive-only serial i/o shift register 1 sioe1 r { 00h fffff914h clocked serial interfac e transmit buffer register 1 sotb1 r/w { 00h fffffa00h asynchronous serial interface mode register 0 asim0 r/w { { 01h fffffa02h receive buffer register 0 rxb0 r { ffh fffffa03h asynchronous serial interf ace status register 0 asis0 r { 00h fffffa04h transmit buffer register 0 txb0 r/w { ffh fffffa05h asynchronous serial interface transmit status register 0 asif0 r { { 00h fffffa06h clock select register 0 cksr0 r/w { 00h fffffa07h baud rate generator control register 0 brgc0 r/w { ffh fffffa10h aynchronous serial interface mode register 1 asim1 r/w { { 01h fffffa12h receive buffer register 1 rxb1 r { ffh fffffa13h asynchronous serial interf ace status register 1 asis1 r { 00h fffffa14h transmit buffer register 1 txb1 r/w { ffh fffffa15h aynchronous serial interface transmit status register 1 asif1 r { { 00h fffffa16h clock select register 1 cksr1 r/w { 00h fffffa17h baud rate generator control register 1 brgc1 r/w { ffh
chapter 3 cpu function 72 user's manual u14980ej2v1ud 3.4.9 specific registers specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. the v850e/m a2 has two specific registers, the power save control register (psc) (refer to 9.5.2 (3) power save control register (psc) ) and clock control register (ckc) (refer to 9.3.4 clock control register (ckc) ). disable dma transfer when writing to a specific register. there are also two protection regist ers supporting write operations for spec ific registers to avoid an unexpected stoppage of the app lication system due to errone ous program execution. these two registers are the command register (prcmd) and peripheral command register (phcmd) (refer to 9.5.2 (2) command register (prcmd) and 9.3.3 peripheral command register (phcmd) ). 3.4.10 system wait control register (vswc) the system wait control regist er (vswc) is a register t hat controls the bus access wa it for the on-chip peripheral i/o registers. access to on-chip peripheral i/o registers is made in 3 clocks (without wait), however , in the v850e/ma2, waits may be required depending on the operating frequency. set the values described in the table below to the vswc register in accordance with the operating frequency used. this register can be read/written in 8-bit uni ts (address: fffff06eh, initial value: 77h). operating frequency (f xx ) set value of vswc number of waits fo r on-chip peripheral i/o register access 4 mhz f xx < 33 mhz 11h 2 33 mhz f xx 40 mhz 12h 3 remark if the timing of changing a count value conflicts wit h the timing of accessing a register when accessing a register with status flags that indi cate the status of the internal peri pheral functions (such as asifn) or a register that indicates the count va lue of a timer (such as tmcn), the register access is retried. as a result, it may take lon ger to access an internal peripheral i/o register. 3.4.11 cautions when using the v850e/ma2, the following registers must be set in the beginning. ? system wait control register (vswc) (refer to 3.4.10 system wait control register (vswc) ) ? clock control register (ckc) (refer to 9.3.4 clock contro l register (ckc) ) after setting vswc and ckc, set other registers if necessary. to use the external bus, initialize each register in the following sequence after setting the above registers. <1> set each pin to the control mode by setting each port-related register. <2> select a chip select space by using chip area select control register n (cscn) (n = 0, 1). <3> specify the type of memory of each chip select space by using bus cycle type configuration register n (bctn).
73 user's manual u14980ej2v1ud chapter 4 bus control function the v850e/ma2 is provided with an exte rnal bus interface function by whic h external i/o and memories, such as rom and ram, can be connected. 4.1 features ? 16-bit/8-bit data bus sizing function 4-space chip select function wait function programmable wait function, through which up to 7 wait states can be inserted for each memory block external wait function via wait pin idle state insertion function bus mastership arbitration function bus hold function external device connection enabled via bus control/port alternate function pins
chapter 4 bus control function 74 user's manual u14980ej2v1ud 4.2 bus control pins the following pins are used for connection to external devices. bus control pin (function when in control mode) func tion when in port mode register for port/control mode switching data bus (d0 to d15) pdl0 to pdl15 (port dl) pmcdl address bus (a0 to a15) pal0 to pal15 (port al) pmcal address bus (a16 to a24) pah0 to pah8 (port ah) pmcah chip select (cs0, cs3, cs4, cs7) pcs0, pcs3, pcs4, pcs7 (port cs) pmccs sdram sync control (sdcke, sdclk) pcd0, pcd1 (port cd) byte access control/sdram control (lbe/sdcas, ube/sdras) pcd2, pcd3 (port cd) pmccd read/write control (lwr/ldqm, uwr/udqm, rd, we) pct0, pct1, pct4, pct5 (port ct) pmcct external wait control (wait) pcm0 (port cm) internal system clock (clkout) pcm1 (port cm) bus hold control (hldrq, hldak) pcm2, pcm3 (port cm) dram refresh control (refrq) pcm4 (port cm) pmccm remark when the system is reset, each bus control pin becomes unconditionally valid. (however, d8 to d15 are valid only in romless mode 0.) 4.2.1 pin status during intern al ram and peripheral i/o access while accessing internal ram, the address bus becomes undefined, and the data bus is not output and enters the high-impedance state. the external bus control signals become inactive. while accessing peripheral i/o, the address bus outputs the address data of the on-chip peripheral i/o currently being accessed. the data bus enter s the output state when write-acce ssing the peripheral i/o, and the high- impedance state when read-accessing th e peripheral i/o. the external bu s control signals become inactive.
chapter 4 bus control function 75 user's manual u14980ej2v1ud 4.3 memory block function the 80 mb memory space is divided into memory blocks of 2 mb and 32 mb units. the programmable wait function and bus cycle operat ion mode can be indep endently controlled for each block. the area that can be used as program area is the space of the 8 mb of addresses 0000000h to 07fffffh and internal ram area. fffffffh fffffffh on-chip peripheral i/o area (4 kb) internal ram area (12 kb note 1 ) external memory area external memory area fffc000h fe00000h fdfffffh ffff000h fffefffh fc00000h fbfffffh fa00000h f9fffffh f800000h f7fffffh c000000h bffffffh a000000h 9ffffffh 8000000h 7ffffffh 6000000h 5ffffffh 4000000h 3ffffffh 0800000h 07fffffh 0600000h 05fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h block 1 (2 mb) block 0 (2 mb) block 2 (2 mb) block 3 (2 mb) 32 mb 32 mb not used area not used area block 5 (2 mb) block 6 (2 mb) block 4 (2 mb) block 7 (2 mb) 3ffffffh on-chip peripheral i/o area (4 kb note 2 ) internal ram area (12 kb note 1 ) 3ffc000h 3fff000h 3ffefffh cs7 area 3 area 2 area 1 area 0 cs4 cs3 cs0 notes 1. 4 kb 2. this area is access-prohibited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh.
chapter 4 bus control function 76 user's manual u14980ej2v1ud 4.3.1 chip select control function of the 80 mb memory area, the lo wer 8 mb (0000000h to 07fffffh) and the higher 8 mb (f800000h to fffffffh) can be divided into 2 mb memory blocks by chip area selection control regi sters 0 and 1 (csc0, csc1) to control the chip select signal. the memory area can be effectively used by dividing it into memory blocks using the chip select control function. the priority order is described below. (1) chip area selection control registers 0, 1 (csc0, csc1) these registers can be read/written in 16-bit units and become valid by setting each bit to 1. caution write to the csc0 and csc1 registers af ter reset, and then do not change the set value. 15 cs33 csc0 address fffff060h after reset 2c11h 14 cs32 13 cs31 12 cs30 11 1 note 10 1 note 9 0 note 8 0 note 7 0 note 6 0 note 5 0 note 4 1 note 3 cs03 2 cs02 1 cs01 0 cs00 15 cs43 csc1 address fffff062h after reset 2c11h 14 cs42 13 cs41 12 cs40 11 1 note 10 1 note 9 0 note 8 0 note 7 0 note 6 0 note 5 0 note 4 1 note 3 cs73 2 cs72 1 cs71 0 cs70 note the operation of t he system is not guaran teed when a va lue other than the initia l value is set to these bits. bit position bit name function chip select chip select enabled by setting csnm bit to 1. csnm cs operation cs00 cs0 output during block 0 access cs01 cs0 output during block 1 access. cs02 cs0 output during block 2 access. cs03 cs0 output during block 3 access. cs30 to cs33 setting has no meaning. cs40 to cs43 setting has no meaning. cs70 cs7 output during block 7 access. cs71 cs7 output during block 6 access. cs72 cs7 output during block 5 access. cs73 cs7 output during block 4 access. 15 to 12, 3 to 0 csnm (n = 0, 3, 4, 7) (m = 0 to 3)
chapter 4 bus control function 77 user's manual u14980ej2v1ud 4.4 bus cycle type control function in the v850e/ma2, the following external devices ca n be connected directly to each memory block. ? sram, external rom, external i/o ? page rom ? sdram connected external devices are spec ified by bus cycle type c onfiguration regi sters 0, 1 (bct0, bct1). (1) bus cycle type configuration registers 0, 1 (bct0, bct1) these registers can be read/written in 16-bit units. be sure to set bits 14, 10 to 8, 6 to 4, 2, and 1 of the bct0 register and bits 14, 13, 10 to 8, 6 to 4, and 2 of the bct1 register to 0. if they are set to 1, the operation is not guaranteed. caution write to the bct0 and bct1 registers after reset, and then do not change the set value. also, do not access an external memory area other than the one for this initialization routine until the initial setting of the bct0 and bct1 registers is complete. however, it is possible to access external memory areas who se initialization setti ngs are complete.
chapter 4 bus control function 78 user's manual u14980ej2v1ud 15 me3 bct0 csn signal address fffff480h after reset 8888h 14 0 13 bt31 12 bt30 11 me2 10 0 9 0 8 0 7 me1 6 0 5 0 4 0 3 me0 2 0 1 0 0 bt00 cs3 cs0 15 me7 bct1 csn signal address fffff482h after reset 8888h 14 0 13 0 12 bt70 11 me6 10 0 9 0 8 0 7 me5 6 0 5 0 4 0 3 me4 2 0 1 bt41 0 bt40 cs7 cs4 note note note note note make sure that the me1, me2, me5, and me 6 bits are cleared to 0 at initialization. bit position bit name function memory controller enable sets memory controller operation enable for each chip select. men memory controller operation enable 0 operation disabled 1 operation enabled 15, 11, 7, 3 (bct0), 15, 11, 7, 3 (bct1) men (n = 0 to 7) bus cycle type specifies the device to be connected to the csn signal. btn0 external device connecte d directly to csn signal 0 sram, external i/o 1 page rom 0 (bct0), 12 (bct1) btn0 (n = 0, 7) bus cycle type specifies the device to be connected to the csn signal. btn1 btn0 external device connec ted directly to csn signal 0 0 sram, external i/o 0 1 page rom 1 0 setting prohibited 1 1 sdram 13, 12 (bct0), 1, 0 (bct1) btn1, btn0 (n = 3, 4)
chapter 4 bus control function 79 user's manual u14980ej2v1ud 4.5 bus access 4.5.1 number of access clocks the number of basic clocks necessary fo r accessing resources is as follows. bus cycle configuration resource (bus width) instruction fetch operand data access internal ram (32 bits) 1 note 1 note when bus access conflicts with a data access: 2 remark unit: clock/access 4.5.2 bus sizing function the bus sizing function controls the dat a bus width for each cs space. the data bus width is specified by using the bus size configuration register (bsc). (1) bus size configuration register (bsc) this register can be read/ written in 16-bit units. be sure to set bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. write to the bsc register after reset, and then do not change the set value. also, do not access an external memory area other than the one for this initialization routine until the initial setting of the bsc register is complete . however, it is possible to access external memory areas whose initiali zation settings are complete. 2. when the data bus width is specified as 8 bits, only the signals shown below become active. lwr: when accessing sram, external rom, or external i/o (write cycle) 15 0 bsc csn signal address fffff066h after reset note 2 0000h/5555h 14 bs70 13 0 12 0/1 note 1 11 0 10 0/1 note 1 9 0 8 bs40 7 0 6 bs30 5 0 4 0/1 note 1 3 0 2 0/1 note 1 1 0 0 bs00 cs3 cs0 cs4 cs7 notes 1. the operation of the system is not guaranteed when a value other than the initial value is set to these bits. 2. when in rom-less mode 0: 5555h when in rom-less mode 1: 0000h bit position bit name function data bus width sets the data bus width of csn space. bsn0 data bus width of csn space 0 8 bits 1 16 bits 14, 8, 6, 0 bsn0 (n = 0, 3, 4, 7)
chapter 4 bus control function 80 user's manual u14980ej2v1ud 4.5.3 endian control function the endian control function can be used to set processi ng of word data in memory using either the big endian method or the little endian method for each cs space selected with the chip select signal (cs0, cs3, cs4, cs7). switching of the endian method is specified usi ng the endian configuration register (bec). caution in the following areas, the data processing method is fixed to little endian, so the setting of the bec register is invalid. ? on-chip peripheral i/o area ? internal ram area ? on-chip peripheral i/o area and the area identical to the internal ram area, which are located at address 3ffffffh or lower ? program area for external memory (1) endian configuration register (bec) this register can be read/written in 16-bit units. be sure to set bits 15, 13 to 9, 7, and 5 to 1 to 0. if they are set to 1, t he operation is not guaranteed. caution write to the bec register after re set, and then do not change the set value. 15 0 bec csn signal address fffff068h after reset 0000h 14 be70 13 0 12 0 11 0 10 0 9 0 8 be40 7 0 6 be30 5 0 4 0 3 0 2 0 1 0 0 be00 cs3 cs0 cs4 cs7 bit position bit name function big endian specifies the endian method. ben0 endian control 0 little-endian method 1 big-endian method 14, 8, 6, 0 ben0 (n = 0, 3, 4, 7)
chapter 4 bus control function 81 user's manual u14980ej2v1ud figure 4-1. big endian addresses within word 0008h 0009h 000ah 000bh 0004h 0005h 0006h 0007h 0000h 0001h 0002h 0003h 31 24 23 16 15 8 7 0 figure 4-2. little endian addresses within word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 4.5.4 big endian method usage restricti ons in nec electronics development tools (1) when using a debugger (id850) the big-endian method is supported only in the memory window display. (2) when using a compiler (ca850) (a) restrictions in c language (i) there are restrictions for variables allocated to/located/in the big-endian space, as shown below. ? union cannot be used. ? bitfield cannot be used. ? access with cast (changing access size) cannot be used. ? variables with initial values cannot be used. (ii) it is necessary to specify the following optimi zation inhibit options because optimization may cause a change in the access size. ? for global optimization part (opt850)? -wo, -xtb ? for optimization depending on model part (impr 850)? -wi, +arg_reg_opt=off, +stld_trans_opt=off the specification of the optimization inhibit option shown above is not necessary, however, if the access is not an access with cast or with masking/shifting note . note this is on the condition that a pattern that may cause the following optimization is not used. however, because it is very difficult for users to check the patterns comp letely in cases such as when several patterns are mixed (especially for optimization depending on model part), it is recommended that the optimization inhi bit options shown above be specified.
chapter 4 bus control function 82 user's manual u14980ej2v1ud [related global optimization part] ? 1-bit set using bit or int i; i ^=1; ? 1-bit clear using bit and i &= ~1; ? 1-bit not using bit xor i ^= ~1; ? 1-bit test using bit and if(i & 1); [related optimization depending on model part] accessing the same variab le in a different size ? cast ? mask ? shift example int i, *ip; char c; . . . c=*((char*)ip); . . . c = 0xff & i; . . . i = (i<<24) >>24; (b) restrictions in assembly language for variables located in the big endian space, a quasi directive that secures an area of other than byte size (.hword, .word, .float, .shword) is not used.
chapter 4 bus control function 83 user's manual u14980ej2v1ud 4.5.5 bus width the v850e/ma2 accesses peripheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the following shows the operation for each type of access. access all dat a in order starting from the lower order side. (1) byte access (8 bits) (a) when the data bus width is 16 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 byte data 15 8 external data bus 2n + 1 address (b) when the data bus width is 8 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data external data bus 2n address 7 0 7 0 byte data external data bus 2n + 1 address (c) when the data bus width is 16 bits (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 byte data 15 8 external data bus 2n + 1 address
chapter 4 bus control function 84 user's manual u14980ej2v1ud (d) when the data bus width is 8 bits (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data external data bus 2n address 7 0 7 0 byte data external data bus 2n + 1 address (2) halfword access (16 bits) (a) when the bus width is 16 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus 2n address 15 8 2n + 1 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 2 address (b) when the data bus width is 8 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus address 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 2n 7 0 7 0 halfword data 15 8 external data bus address 7 0 7 0 halfword data 15 8 external data bus 2n + 2 address 2n + 1
chapter 4 bus control function 85 user's manual u14980ej2v1ud (c) when the data bus width is 16 bits (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 15 8 2n 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 2 address (d) when the data bus width is 8 bits (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus 2n address 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 external data bus 2n + 2 address
chapter 4 bus control function 86 user's manual u14980ej2v1ud (3) word access (32 bits) (a) when the bus width is 16 bits (little endian) (1/2) <1> access to address 4n 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 <2> access to address 4n + 1 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 23 16 31 24
chapter 4 bus control function 87 user's manual u14980ej2v1ud (a) when the bus width is 16 bits (little endian) (2/2) <3> access to address 4n + 2 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 4n + 5 23 16 31 24 <4> access to address 4n + 3 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 4n + 5 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 6 address 15 8 23 16 31 24
chapter 4 bus control function 88 user's manual u14980ej2v1ud (b) when the data bus width is 8 bits (little endian) (1/2) <1> access to address 4n 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 <2> access to address 4n + 1 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24
chapter 4 bus control function 89 user's manual u14980ej2v1ud (b) when the data bus width is 8 bits (little endian) (2/2) <3> access to address 4n + 2 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 <4> access to address 4n + 3 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 6 address 15 8 23 16 31 24
chapter 4 bus control function 90 user's manual u14980ej2v1ud (c) when the data bus width is 16 bits (big endian) (1/2) <1> access to address 4n 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n + 3 address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 1 address 15 8 4n 23 16 31 24 <2> access to address 4n + 1 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 3 address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 23 16 31 24
chapter 4 bus control function 91 user's manual u14980ej2v1ud (c) when the data bus width is 16 bits (big endian) (2/2) <3> access to address 4n + 2 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n + 5 address 15 8 4n + 4 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 3 address 15 8 4n + 2 23 16 31 24 <4> access to address 4n + 3 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 5 address 15 8 4n + 4 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 6 address 15 8 23 16 31 24
chapter 4 bus control function 92 user's manual u14980ej2v1ud (d) when the data bus width is 8 bits (big endian) (1/2) <1> access to address 4n 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n address 15 8 23 16 31 24 <2> access to address 4n + 1 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 4 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24
chapter 4 bus control function 93 user's manual u14980ej2v1ud (d) when the data bus width is 8 bits (big endian) (2/2) <3> access to address 4n + 2 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 5 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 <4> access to address 4n + 3 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 6 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24
chapter 4 bus control function 94 user's manual u14980ej2v1ud 4.6 wait function 4.6.1 programmable wait function (1) data wait control registers 0, 1 (dwc0, dwc1) to facilitate interfacing with low-speed memory or with i/os , it is possible to insert up to 7 data wait states in the starting bus cycle for each cs space. the number of wait states can be specified by program using data wait control registers 0 and 1 (dwc0, dwc1). just after system reset, all blo cks have 7 data wait states inserted. these registers can be read/written in 16-bit units. be sure to set bits 10 to 8 and 6 to 4 to 1. if they are set to 0, the operation is not guaranteed. cautions 1. the internal ram area is not subj ect to programmable waits and ordinarily no wait access is carried out. the on-chip periphe ral i/o area is also not subject to programmable wait states, with wait control performed by each peripheral func tion only. 2. in the following cases, the settings of registers dwc0 and dwc1 are invalid (wait control is performed by each memory controller). ? page rom on-page access ? sdram access 3. write to the dwc0 and dwc1 registers after reset, and then do not change the set values. also, do not access an external memo ry area other than the one for this initialization routine until the initial se tting of the dwc0 and dwc1 registers is complete. however, it is possible to access external memory areas whose initialization settings are complete.
chapter 4 bus control function 95 user's manual u14980ej2v1ud 15 dwc0 csn signal address fffff484h after reset 7777h 14131211109876543210 0 dw32 dw31 dw30 011101110 dw02 dw01 dw00 0 dw72 dw71 dw70 011101110 dw42 dw41 dw40 cs3 cs0 cs7 cs4 15 dwc1 csn signal address fffff486h after reset 7777h 14131211109876543210 bit position bit name function data wait specifies the number of wait states inserted in the csn space. dwn2 dwn1 dwn0 number of wait states inserted in csn space 0 0 0 not inserted 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 14 to 12, 2 to 0 dwn2 to dwn0 (n = 0, 3, 4, 7)
chapter 4 bus control function 96 user's manual u14980ej2v1ud (2) address setup wait control register (asc) the v850e/ma2 allows insertion of address setup wa it states before the sram /page rom cycle (the setting of the asc register in the sdram cycle is invalid). the number of address setup wait states can be set with the asc register for each cs space. this register can be read/written in 16-bit units. be sure to set bits 13 to 10 and 5 to 2 to 1. if they are set to 0, the oper ation is not guaranteed. cautions 1. during address setup wait, the wait pi n-based external wait f unction is disabled. 2. write to the asc register after reset , and then do not ch ange the set value. 15 ac71 asc csn signal address fffff48ah after reset ffffh 14 ac70 13 1 12 1 11 1 10 1 9 ac41 8 ac40 7 ac31 6 ac30 5 1 4 1 3 1 2 1 1 ac01 0 ac00 cs3 cs0 cs4 cs7 bit position bit name function address cycle specifies the number of address setup wait states inserted before the sram/page rom cycle for each cs space. acn1 acn0 number of wait states 0 0 not inserted 0 1 1 1 0 2 1 1 3 15, 14, 9 to 6, 1, 0 acn1, acn0 (n = 0, 3, 4, 7)
chapter 4 bus control function 97 user's manual u14980ej2v1ud 4.6.2 external wait function when an extremely slow device, i/o, or asynchronous system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (wait) for synchronization with the external device. just as with programmable waits, accessing internal ra m and on-chip peripheral i/o area s cannot be controlled by external waits. the external wait signal can be input asynchronously to cl kout and is sampled at the rising edge of the clock in the t1 and tw states of a bus cycle. if the setup/hold time in the samp ling timing is not satisfied, the wait state may or may not be inserted in the next state. 4.6.3 relationship between programm able wait and external wait a wait cycle is inserted as the result of an or operation between the wait cycle specifi ed by the set value of the programmable wait and the wait cycle controlled by the wait pin. in ot her words, the number of wait cycles is determined by the side with t he greatest number of cycles. wait control programmable wait wait by wait pin for example, if the timings of the pr ogrammable wait and the wait pin signal are as illustrated below, three wait states will be inserted in the bus cycle. figure 4-3. example of wait insertion t1 tw tw tw t2 clkout wait pin wait by wait pin programmable wait wait control remark the circle { indicates the sampling timing
chapter 4 bus control function 98 user's manual u14980ej2v1ud 4.6.4 bus cycles in which wait functi on is valid in the v850e/ma2, the number of waits can be specified a ccording to the memory type specified for each memory block. the following shows t he bus cycles in which the wait function is valid and the re gisters used for wait setting. table 4-1. bus cycles in which wait function is valid programmable wait setting bus cycle type of wait register bit wait count wait from wait pin address setup wait asc acn1, acn0 0 to 3 ? (invalid) sram, external rom, external i/o cycles data access wait dwc0, dwc1 dwn2 to dwn0 0 to 7 (valid) page rom cycle address setup wait asc acn1, acn0 0 to 3 ? (invalid) off page data access wait dwc0, dwc1 dwn2 to dwn0 0 to 7 (valid) on page data access wait prc prw2 to prw0 0 to 7 (valid) sdram cycle row address precharge scrm bcw1m, bcw0m 1 to 3 ? (invalid) remark n = 0, 3, 4, 7, m = 3, 4
chapter 4 bus control function 99 user's manual u14980ej2v1ud 4.7 idle state insertion function to facilitate interfacing with low-speed me mory devices, an idle state (ti) can be inserted into the current bus cycle after the t2 state to meet the data output float delay time (t df ) on memory read access for each cs space. the bus cycle following the t2 state starts a fter the idle state is inserted. an idle state is inserted in the timing shown below. ? after read/write cycles for sram, external i/o, or external rom ? after a read cycle for page rom ? after a read cycle for sdram the idle state insertion setting c an be specified by program using the bus cycle control register (bcc). immediately after the system reset, idle state insertion is aut omatically programmed for all memory blocks. for the timing when an idle state is inserted, refer to the access timings of each memory in chapter 5. (1) bus cycle control register (bcc) this register can be read/written in 16-bit units. be sure to set bits 13 to 10 and 5 to 2 to 1. if they are set to 0, the oper ation is not guaranteed. cautions 1. the internal ram area and on-chip peripheral i/o area are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set value. also, do not access an external memory area other than the one for this initialization routine until the initial setting of the bcc register is comple te. however, it is possible to access external memory areas whose initializa tion settings are complete. 15 bc71 bcc csn signal address fffff488h after reset ffffh 14 bc70 13 1 12 1 11 1 10 1 9 bc41 8 bc40 7 bc31 6 bc30 5 1 4 1 3 1 2 1 1 bc01 0 bc00 cs3 cs0 cs4 cs7 bit position bit name function data cycle specifies the insertion of an idle state in the csn space. bcn1 bcn0 idle state in csn space 0 0 not inserted 0 1 1 1 0 2 1 1 3 15, 14, 9 to 6, 1, 0 bcn1, bcn0 (n = 0, 3, 4, 7)
chapter 4 bus control function 100 user's manual u14980ej2v1ud 4.8 bus hold function 4.8.1 function outline if pins pcm2 and pcm3 are specified in the contro l mode, the hldak and hldrq functions become valid. if it is determined that the hldrq pin has become active (low level) as a bus mastership request from another bus master, the external address/data bus and each strobe pin ar e shifted to high impedance and then released (bus hold state). if the hldrq pin becomes inactive (high level) an d the bus mastership request is canceled, driving of these pins begins again. during the bus hold period, the internal operations of the v850e/ma2 continue until the external memory or a peripheral i/o register is accessed. the bus hold state can be known by the hldak pin becoming active (low level). the period from when the hldrq pin becomes active (low level) to when the hldak pin becomes acti ve (low level) is at least 2 clocks. in a multiprocessor configurati on, etc., a system with multiple bus masters can be configured. state data bus width access type timing in which bus hold request cannot be acknowledged word access for even address between first and second accesses between first and second accesses word access for odd address between second and third accesses 16 bits halfword access for odd address between first and second accesses between first and second accesses between second and third accesses word access between third and forth accesses cpu bus lock 8 bits halfword access between first and second accesses read modify write access of bit manipulation instruction ? ? between read access and write access cautions 1. when an external bus master accesses sdram during a bus hold state, make sure that the external bus master executes the all bank precharge command. the cpu always executes the all bank precharge command to release a bus hold state. in a bus hold state, do not allow an external bus master to change the sdram command register value. 2. the hldrq function is invalid during a r eset period. the hldak pin becomes active either immediately after or after the insertion of a 1-clock address cycle from when the reset pin is set to inactive following the simultane ous activation of the reset and hldrq pins. when a bus master other than the v850e/ma2 is extern ally connected, use the reset signal for bus arbitration at power-on.
chapter 4 bus control function 101 user's manual u14980ej2v1ud 4.8.2 bus hold procedure the procedure of the bus hold function is illustrated below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests held pending <3> end of current bus cycle <4> transition to bus idle state <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> releases pending bus cycle start request <9> start of bus cycle normal state bus hold state normal state hldak (output) hldrq (input) <1> <2> <3><4> <5> <6> <7><8><9> 4.8.3 operation in power save mode in the software stop or idle mode, the internal system clock is stopped. consequently , the bus hold state is not acknowledged and set since the hldrq pin cannot be acknowledged even if it becomes active. in the halt mode, the hldak pin immediately becomes active when the hldrq pin becomes active, and the bus hold state is set. when the hldrq pin becomes inactive a fter that, the hldak pin also becomes inactive. as a result, the bus hold state is cleared and the halt mode is set again.
chapter 4 bus control function 102 user's manual u14980ej2v1ud 4.8.4 bus hold timing (sram) (1) sram (when read, no idle state inserted) t1 t2 undefined lwr (output) uwr (output) we (output) rd (output) csn (output) hldrq (input) hldak (output) a0 to a24 (output) clkout (input) th th ti note ti note lbe (output) wait (input) d0 to d15 (i/o) data ube (output) address note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 4 bus control function 103 user's manual u14980ej2v1ud (2) sram (when written, three idle states inserted) t1 t2 undefined lwr (output) uwr (output) we (output) rd (output) csn (output) hldrq (input) hldak (output) a0 to a24 (output) clkout (input) th th ti note 1 ti note 1 ti note 1 ti note 2 ti note 2 lbe (output) wait (input) d0 to d15 (i/o) ube (output) address data notes 1. this idle state (ti) is inserted by means of a bcc register setting. 2. this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 4 bus control function 104 user's manual u14980ej2v1ud 4.8.5 bus hold timing (sdram) (1) sdram (when read, latency = 2, no idle state inserted) tpre note 2 tw tact d0 to d15 (i/o) we (output) rd (output) sdcas (output) sdras (output) csn (output) a0 to a9 (output) a10 (output) bank address (output) sdclk (output) tread tlate tbcw tw tlate th th ti note 1 ti note 1 hldrq (input) hldak (output) note 3 (output) sdcke (output) ldqm (output) udqm (output) bcw address address address column address address data bank address row address row address undefined undefined undefined undefined h notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. the all bank precharge command is always executed. 3. addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 3, 4
chapter 4 bus control function 105 user's manual u14980ej2v1ud (2) sdram (when read, latency = 2, three idle states inserted) tpre ( note 3 ) tw tact d0 to d15 (i/o) we (output) rd (output) sdcas (output) sdras (output) csn (output) a0 to a9 (output) a10 (output) bank address (output) sdclk (output) tread tlate tlate tbcw tw th th ti note 1 ti note 1 ti note 1 ti note 2 ti note 2 hldrq (input) hldak (output) note 4 (output) sdcke (output) ldqm (output) udqm (output) h bcw address address address address bank address row address row address column address undefined undefined undefined undefined data notes 1. this idle state (ti) is inserted by means of a bcc register setting. 2. this idle state (ti) is independ ent of the bcc register setting. 3. the all bank precharge command is always executed. 4. addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 3, 4
chapter 4 bus control function 106 user's manual u14980ej2v1ud (3) sdram (when written) tpre ( note 2 ) tw tact d0 to d15 (i/o) we (output) rd (output) sdcas (output) sdras (output) csn (output) a0 to a9 (output) a10 (output) bank address (output) sdclk (output) twpre twe tbcw twr tw th th ti note 1 ti note 1 hldrq (input) hldak (output) note 3 (output) sdcke (output) ldqm (output) udqm (output) h address address address address bank address row address row address column address undefined undefined undefined undefined data bcw notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. the all bank precharge command is always executed. 3. addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 3, 4
chapter 4 bus control function 107 user's manual u14980ej2v1ud (4) sdram (when written, when bus hold request ackno wledged during on-page access) tpre ( note 2 ) tw tact d0 to d15 (i/o) we (output) rd (output) sdcas (output) sdras (output) csn (output) a0 to a9 (output) a10 (output) bank address (output) sdclk (output) twpre twe tbcw twr twr tw th th ti note 1 ti note 1 hldrq (input) hldak (output) note 3 (output) sdcke (output) ldqm (output) udqm (output) h address address bank address row address undefined undefined undefined undefined data data bcw address address address row address column address column address notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. the all bank precharge command is always executed. 3. addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 3, 4
chapter 4 bus control function 108 user's manual u14980ej2v1ud 4.9 bus priority order there are five external bus cycles: bus hold, instructio n fetch, operand data access, dma cycle, and refresh cycle. in order of priority, bus hold is t he highest, followed by the refresh cycle, dma cycle, operand data access, and instruction fetch, in that order. an instruction fetch may be inserted between a read acce ss and write access during a read modify write access. also, an instruction fetch may be inserted between bus accesses when a cpu bus clock is used. table 4-2. bus priority order priority order external bus cycle bus master high bus hold external device refresh cycle sdram controller dma cycle dma controller operand data access cpu low instruction fetch cpu
chapter 4 bus control function 109 user's manual u14980ej2v1ud 4.10 boundary operation conditions 4.10.1 program space (1) branching to the on-chip peripheral i/o area or successive fetches from the internal ram area to the on-chip peripheral i/o area are prohibited. if the above is perf ormed (branching or successive fetch), an undefined data is fetched, and fetching from the external memory is not performed. (2) if a branch instruction exists at the upper limit of th e internal ram area, a pre-fetch operation (invalid fetch) that straddles over the on-chip peripheral i/o area does not occur. 4.10.2 data space the v850e/ma2 is provided with an address misalign function. through this function, regardless of the data format (wor d data or halfword data), data can be allocated to all addresses. however, in the case of word data and halfword data, if the data is not s ubject to boundary alignment, the bus cycle will be generated at least 2 times and bus efficiency will drop. (1) in the case of halfword-length data access when the address's lsb is 1, the byte-l ength bus cycle will be generated 2 times. (2) in the case of word-length data access (a) when the address's lsb is 1, bus cycles will be generated in the order of byte-length bus cycle, halfword-length bus cycle, an d byte-length bus cycle. (b) when the address's lowest 2 bits are 10, the halfword-length bus cycle will be generated 2 times.
110 user's manual u14980ej2v1ud chapter 5 memory ac cess control function 5.1 sram, external rom, external i/o interface 5.1.1 features ? sram is accessed in a minimum of 2 states. ? up to 7 states of programmable data waits can be inserted by setting the dwc0 and dwc1 registers. ? data wait can be controlled via wait pin input. ? up to 3 idle states can be inserted after a read/write cycle by setting the bcc register. ? up to 3 address setup wait states can be inserted by setting the asc register.
chapter 5 memory access control function 111 user's manual u14980ej2v1ud 5.1.2 sram connection examples of connection to sram are shown below. figure 5-1. examples of connection to sram (1/2) (a) when data bus width is 8 bits a0 to a16 d1 to d8 1 mb sram (128 kwords 8 bits) cs oe we a1 to a17 d0 to d7 csn rd lwr d8 to d15 v850e/ma2 uwr a0 to a16 d1 to d8 1 mb sram (128 kwords 8 bits) cs oe we (b) when data bus width is 16 bits 2 mb sram (256 kwords 16 bits) a1 to a17 a0 to a16 v850e/ma2 d0 to d15 d1 to d16 csn cs lwr uwruwr lbelbe lbe ube ube rd oe we remark n = 0, 3, 4, 7
chapter 5 memory access control function 112 user's manual u14980ej2v1ud figure 5-1. examples of connection to sram (2/2) (c) mixture of sram (256 kwords 16 bits) and sdram (1 mword 16 bits) a0 to a16 d1 to d16 2 mb sram (256 kwords 16 bits) cs oe we lbe ube v850e/ma2 a0 to a11 a12, a13 dq0 to dq15 64 mb sdram (1 mword 16 bits 4 banks) cs ldqm udqm we cke clk ras cas a1 to a17, a21, a22 d0 to d15 csn rd ldqm/lwr udqm/uwr a1 to a12 a21 note , a22 we sdcke sdclk sdras/ube sdcas/lbe csm a1 to a17 note the address signals used depend on the sdram model. remark n = 0, 3, 4, 7, m = 3, 4 (n m)
chapter 5 memory access control function 113 user's manual u14980ej2v1ud 5.1.3 sram, external rom, external i/o access figure 5-2. sram, external rom, external i/o access timing (1/6) (a) when read t1 t2 address data wait (input) d0 to d15 (i/o) lwr (output) uwr (output) we (output) rd (output) csn (output) lbe (output) ube (output) a0 to a24 (output) clkout (output) data address tw t2 t1 remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 5 memory access control function 114 user's manual u14980ej2v1ud figure 5-2. sram, external rom, external i/o access timing (2/6) (b) when read (address setup wait, idle state insertion) tasw t1 address data wait (input) d0 to d15 (i/o) lwr (output) uwr (output) we (output) rd (output) csn (output) a0 to a24 (output) clkout (output) ti t2 lbe (output) ube (output) remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 5 memory access control function 115 user's manual u14980ej2v1ud figure 5-2. sram, external rom, external i/o access timing (3/6) (c) when written t1 t2 address data wait (input) d0 to d15 (i/o) lwr (output) uwr (output) we (output) rd (output) a0 to a24 (output) clkout (output) data address tw t2 t1 csn (output) lbe (output) ube (output) remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 5 memory access control function 116 user's manual u14980ej2v1ud figure 5-2. sram, external rom, external i/o access timing (4/6) (d) when written (address set up wait, idle state insertion) tasw t1 address data wait (input) d0 to d15 (i/o) lwr (output) uwr (output) we (output) rd (output) a0 to a24 (output) clkout (output) ti t2 csn (output) lbe (output) ube (output) remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 5 memory access control function 117 user's manual u14980ej2v1ud figure 5-2. sram, external rom, external i/o access timing (5/6) (e) for read write operation t1 t2 address address data data wait (input) d0 to d15 (i/o) lwr (output) uwr (output) we (output) rd (output) a0 to a24 (output) clkout (output) t2 t1 csn (output) lbe (output) ube (output) remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 5 memory access control function 118 user's manual u14980ej2v1ud figure 5-2. sram, external rom, external i/o access timing (6/6) (f) for write read operation t1 t2 data wait (input) d0 to d15 (i/o) lwr (output) uwr (output) we (output) rd (output) a0 to a24 (output) clkout (output) t2 t1 csn (output) lbe (output) ube (output) data address address remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 5 memory access control function 119 user's manual u14980ej2v1ud 5.2 page rom controller (romc) the page rom controller (romc) is provided for a ccessing rom (page rom) with a page access function. addresses are compared with the immediately preceding bus cycle and wait control fo r normal access (off-page) and page access (on-page) is executed. this controll er can handle page widths from 8 to 128 bytes. 5.2.1 features ? direct connection to 8-bit/16-bit page rom supported ? for 16-bit bus width: 4/8/16/32/64-word page access supported for 8-bit bus width: 8/16/32/6 4/128-word page access supported ? page rom is accessed in a minimum of 2 states. ? on-page judgment function ? addresses to be compared can be changed by setting the prc register. ? up to 7 states of programmable data waits can be inserted during an on-page cycle by setting the prc register. ? up to 7 states of programmable data waits can be inse rted during an off-page cycle by setting the dwc0 and dwc1 registers. ? waits can be controlled via wait pin input.
chapter 5 memory access control function 120 user's manual u14980ej2v1ud 5.2.2 page rom connection examples of connection to page rom are shown below. figure 5-3. examples of connection to page rom (a) when data bus width is 16 bits a0 to a19 o1 to o16 ce oe 16 mb page rom (1 mword 16 bits) a1 to a20 d0 to d15 csn rd v850e/ma2 (b) when data bus width is 8 bits a0 to a20 o1 to o8 ce oe 16 mb page rom (2 mwords 8 bits) a1 to a21 d0 to d7 csn rd d8 to d15 v850e/ma2 a0 to a20 o1 to o8 ce oe 16 mb page rom (2 mwords 8 bits) remark n = 0, 3, 4, 7
chapter 5 memory access control function 121 user's manual u14980ej2v1ud 5.2.3 on-page/off-page judgment whether a page rom cycle is on-page or off-page is jud ged by latching the address of the previous cycle and comparing it with the addre ss of the current cycle. through the page rom configuration register (prc), acco rding to the configuration of the connected page rom and the number of continuously readable bits, one of the addresses (a3 to a6) is set as the masking address (no comparison is made). figure 5-4. on-page/off-page judgmen t during page rom connection (1/2) (a) in case of 16 mb (1 m 16 bits) page rom (4-word page access) a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a2 a1 a1 a0 a0 internal address latch (immediately preceding address) v850e/ma2 address output page rom address a19 off-page address on-page address continuous reading possible: 16-bit data bus width 4 words a6 a5 a4 a3 a2 ma6 0 ma5 0 ma4 0 ma3 0 prc register setting comparison
chapter 5 memory access control function 122 user's manual u14980ej2v1ud figure 5-4. on-page/off-page judgmen t during page rom connection (2/2) (b) in case of 16 mb (1 m 16 bits) page rom (8-word page access) a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a2 a1 a1 a0 a0 internal address latch (immediately preceding address) v850e/ma2 address output page rom address a19 off-page address on-page address continuous reading possible: 16-bit data bus width 8 words a6 a5 a4 a3 a2 ma6 0 ma5 0 ma4 0 ma3 1 prc register setting comparison ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (c) in case of 32 mb (2 m 16 bits) page rom (16-word page access) a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a2 a1 a1 a0 a0 internal address latch (immediately preceding address) v850e/ma2 address output page rom address a19 off-page address on-page address continuous reading possible: 16-bit data bus width 16 words a6 a5 a4 a3 a2 ma6 0 ma5 0 ma4 1 ma3 1 prc register setting comparison ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 5 memory access control function 123 user's manual u14980ej2v1ud 5.2.4 page rom configuration register (prc) this register specifies whether p age rom cycle on-page access is enable d or disabled. if on-page access is enabled, the masking address (no comparison is made) out of the addresses (a3 to a6) corresponding to the configuration of the connected page ro m and the number of bits that can be read continuously, as well as the number of waits corresponding to t he internal system clock, are set. this register can be read/written in 16-bit units. caution write to the prc register after reset, an d then do not change the set value. also, do not access an external memory area other than the one for this initializat ion routine until the initial setting of the prc register is comple te. however, it is possible to access external memory areas whose initiali zation settings are complete. 15 0 prc address fffff49ah after reset 7000h 14 prw2 13 prw1 12 prw0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ma6 2 ma5 1 ma4 0 ma3 bit position bit name function page-rom on-page wait control sets the number of waits correspondi ng to the internal system clock. the number of waits set by these bits is in serted only for on-page access. for off-page access, the waits set by registers dwc0 and dwc1 are inserted. prw2 prw1 prw0 number of inserted wait cycles 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 14 to 12 prw2 to prw0 mask address each respective address (a6 to a3) correspondi ng to ma6 to ma3 is masked (masked by 1). the masked address is not subject to comparison during on/off-page judgment, and is set according to the number of continuously readable bits. ma6 ma5 ma4 ma3 number of continuously readable bits 0 0 0 0 4 words 16 bits (8 words 8 bits) 0 0 0 1 8 words 16 bits (16 words 8 bits) 0 0 1 1 16 words 16 bits (32 words 8 bits) 0 1 1 1 32 words 16 bits (64 words 8 bits) 1 1 1 1 64 words 16 bits (128 words 8 bits) other than above setting prohibited 3 to 0 ma6 to ma3
chapter 5 memory access control function 124 user's manual u14980ej2v1ud 5.2.5 page rom access figure 5-5. page rom access timing (1/4) (a) when read (halfword/word access with 8-bit bus width or word access with 16-bit bus width) t1 tw off-page address data wait (input) d0 to d15 (i/o) d0 to d7 (i/o) lwr (output) uwr (output) we (output) rd (output) csn (output) a0 to a24 (output) clkout (output) data on-page address to1 to2 t2 note note when accessing a word boundary with an 8-bit bus width. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 5 memory access control function 125 user's manual u14980ej2v1ud figure 5-5. page rom access timing (2/4) (b) when read (byte access with 8-bit bus width or byte/half- word access with 16-bit bus width) t1 tw off-page address data wait (input) d0 to d15 (i/o) d0 to d7 (i/o) lwr (output) uwr (output) we (output) rd (output) csn (output) a0 to a24 (output) clkout (output) data on-page address to1 to2 t2 remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 5 memory access control function 126 user's manual u14980ej2v1ud figure 5-5. page rom access timing (3/4) (c) when read (address setup wait, idle state insertion) (halfword/word access with 8- bit bus width or word access with 16-bit bus width) tasw t1 off-page address data wait (input) d0 to d15 (i/o) d0 to d7 (i/o) lwr (output) uwr (output) we (output) rd (output) csn (output) a0 to a24 (output) clkout (output) data on-page address tasw to1 to2 ti t2 remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 5 memory access control function 127 user's manual u14980ej2v1ud figure 5-5. page rom access timing (4/4) (d) when read (address setup wait, idle state insertion) (byte access with 8-bit bus width or byte/halfword access with 16-bit bus width) tasw t1 off-page address data wait (input) d0 to d15 (i/o) d0 to d7 (i/o) lwr (output) uwr (output) we (output) rd (output) csn (output) a0 to a24 (output) clkout (output) data on-page address tasw to1 to2 ti t2 remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7
chapter 5 memory access control function 128 user's manual u14980ej2v1ud 5.3 sdram controller 5.3.1 features ? burst length: 1 ? wrap type: sequential ? cas latency: 2 and 3 supported ? 4 types of sdram can be assigned to 4 memory blocks. ? row and column address multiplex widths can be changed. ? waits (0 to 3 waits) can be inserted between t he bank active command and the read/write command. ? supports cbr refresh and cbr self refresh. 5.3.2 sdram connection an example of connection to sdram is shown below. figure 5-6. example of connection to sdram a0 to a11 a12, a13 dq0 to dq15 clk cke cs ras cas ldqm udqm we 64 mb sdram (1 mword 16 bits 4 banks) a1 to a12 a21, a22 note d0 to d15 sdclk sdcke cs3, cs4 sdras sdcas ldqm udqm we v850e/ma2 note the address signals to be used differ depending on the sdram product.
chapter 5 memory access control function 129 user's manual u14980ej2v1ud 5.3.3 address multiplex function depending on the value of the saw0n and saw1n bits in sdram configuration regi ster n (scrn), the row address output in the sdram cycle is multiplexed as shown in figure 5-7 (a) (n = 3, 4). depending on the value of the sso0n and sso1n bits, the column address output in the sdram cycle is multiplexed as shown in figure 5-7 (b) (n = 3, 4). in figures 5-7 (a) and (b), a0 to a24 indicate the addresses output from the cpu, and a0 to a24 indicate the address pins of the v850e/ma2. figure 5-7. row address/co lumn address output (1/2) (a) row address output a15 a25 a14 a24 a13 a23 a24 to a18 address pin a24 to a18 row address (saw1n, saw0n = 10) a17 a17 a16 a16 a12 a22 a11 a21 a10 a20 a9 a19 a8 a18 a7 a17 a6 a16 a5 a15 a4 a14 a3 a13 a2 a12 a1 a11 a0 a10 a24 a23 a22 a24 to a18 row address (saw1n, saw0n = 01) a17 a25 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a23 a22 a21 a24 to a18 row address (saw1n, saw0n = 00) a25 a24 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 remark n = 3, 4 (b) column address output (using all bank precharge command) a15 a15 a14 a14 a13 a13 a24 to a18 address pin a24 to a18 column address (sso1n, sso0n = 00) a17 a17 a16 a16 a12 a12 a11 a11 a10 1 a9 a9 a8 a8 a7 a7 a6 a6 a5 a5 a4 a4 a3 a3 a2 a2 a1 a1 a0 a0 a15 a14 a13 a24 to a18 column address (sso1n, sso0n = 01) a17 a16 a12 1 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 remark n = 3, 4 (c) column address output (using register write command) a15 0 a14 0 a13 0 a24 to a18 address pin 0 column address (sso1n, sso0n = 00) a17 0 a16 0 a12 0 a11 0 a10 0 a9 0 a8 0 a7 0 a6 ltm2 a5 ltm1 a4 ltm0 a3 0 a2 0 a1 0 a0 0 000 0 column address (sso1n, sso0n = 01) 00 0 0 000 ltm2 ltm1 ltm0 00000 remark n = 3, 4
chapter 5 memory access control function 130 user's manual u14980ej2v1ud figure 5-7. row address/colu mn address output (2/2) (d) column address output (using read/write command) a15 a15 a14 a14 a13 a13 a24 to a18 address pin a24 to a18 column address (sso1n, sso0n = 00) a17 a17 a16 a16 a12 a12 a11 a11 a10 0 a9 a9 a8 a8 a7 a7 a6 a6 a5 a5 a4 a4 a3 a3 a2 a2 a1 a1 a0 a0 a15 a14 a13 a24 to a18 column address (sso1n, sso0n = 01) a17 a16 a12 0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 remark n = 3, 4
chapter 5 memory access control function 131 user's manual u14980ej2v1ud 5.3.4 sdram configuration registers 3, 4 (scr3, scr4) these registers specify the number of waits and the address multiplex width. scr3 and scr4 corresponds to cs3 and cs4. for example, to connect sdram to cs3, set scr3. these registers can be read/written in 16-bit units. cautions 1. the sdram read/write cycle is not gene rated prior to executing the power-on cycle. access sdram after waiting 20 clocks following a program write to the scr register. to write to the scr register again following access to sdram , clear the men bit of the bct0 and bct1 registers to 0, and then set them to 1 ag ain before performing access (n = 0 to 7). 2. do not execute continuous instructions to write to the scr register. be sure to insert another instruction between commands to write to the scr register. (1/2) 15 address fffff4ach after reset 0000h 14131211109876543210 0 scr3 ltm23 ltm13 ltm03 0000 bcw13 bcw03 sso13 sso03 raw13 raw03 saw13 saw03 0 scr4 fffff4b0h 0000h ltm24 ltm14 ltm04 0000 bcw14 bcw04 sso14 sso04 raw14 raw04 saw14 saw04 bit position bit name function latency sets the cas latency value for reading. ltm2n ltm1n ltm0n latency 0 0 3 0 1 0 2 0 1 1 3 1 setting prohibited 14 to 12 ltm2n to ltm0n (n = 3, 4) bank active command wait control specifies the number of wait states inserted from the bank active command to a read/write command, or from the precharge command to the bank active command. bcw1n bcw0n number of wait states inserted 0 0 1 (at least 1 wait is always inserted) 0 1 1 1 0 2 1 1 3 7, 6 bcw1n, bcw0n (n = 3, 4) remark : don't care
chapter 5 memory access control function 132 user's manual u14980ej2v1ud (2/2) bit position bit name function sdram shift width on-page control specifies the address shift width during on-page judgment. when the external data bus width is 8 bits: set sso1n, sso0n = 00b when the external data bus width is 16 bits: set sso1n, sso0n = 01b sso1n sso0n address shift width 0 0 8 bits 0 1 16 bits 1 0 setting prohibited 1 1 setting prohibited 5, 4 sso1n, sso0n (n = 3, 4) row address width control specifies the row address width. raw1n raw0n row address width 0 0 11 0 1 12 1 0 setting prohibited 1 1 setting prohibited 3, 2 raw1n, raw0n (n = 3, 4) caution memories with a row address width above 13 cannot be controlled. row address multiplex width control specifies the address multiplex width during sdram access. saw1n saw0n address multiplex width 0 0 8 0 1 9 1 0 10 1 1 setting prohibited 1, 0 saw1n, saw0n (n = 3, 4)
chapter 5 memory access control function 133 user's manual u14980ej2v1ud 5.3.5 sdram access during power-on or a refresh operation, the all bank precharge command is always issued for sdram. when accessing sdram after that, therefore, the active command and read/write command are issued in that order (see <1> in figure 5-8). if a page change occurs following this, the prechar ge command, active command, and read/write command are issued in that order (see <2> in figure 5-8). if a bank change occurs, the active command and read/write command for the bank to be accessed next are issued in that order. following this read/write command, the precharge command for the bank that was accessed before the bank currently being accessed will be issued (see <3> in figure 5-8). figure 5-8. state transition of sdram access <1> <3> <2> all bank pre-charge command (power on/refresh) bank a active command bank a precharge command bank a active command bank a active command bank b active command bank b read/write command bank a read/write command bank a read/write command read/write command read/write command (on-page access) (page change) (bank change) (bank change) bank a precharge command
chapter 5 memory access control function 134 user's manual u14980ej2v1ud (1) sdram single read cycle the sdram single read cycle is a cycle for reading from sdram by executing a load instruction (ld) for the sdram area, by fetching an instruction, or by 2-cycle dma transfer. in the sdram single read cycle, the active command (act) and read command (rd) are issued for sdram in that order. during on-page access, however, on ly the read command is issued and the precharge command and active command are not issued. when a page change occurs in the same bank, the precharge command (pre) is issued before the active command. the timing to sample data is synchronized with rising of the udqm and ldqm signals. a one-state tw cycle is always inserted immediately bef ore the all read command, which is activated by the cpu. the number of idle states set by t he bus cycle control register (bcc) are inserted before the read cycle (no idle state is inserted, however, if bcn1 and bcn0 are 00 ) (n = 3, 4). the timing charts of the sdram single read cycle are shown below. caution when executing a write acces s to sram or external i/o afte r read accessing sdram, data conflict may occur depending on the sdram data output float delay time. in such a case, avoid data conflict by inserting an idle stat e in the sdram space via a setting in the bcc register.
chapter 5 memory access control function 135 user's manual u14980ej2v1ud figure 5-9. sdram single read cycle (1/3) (a) during off-page access (when latency = 2) tact act rd tw tread tlate tlate data address address address address column address row address address address bank address address row address sdclk (output) sdcke (output) h command sdras (output) sdcas (output) cs3, cs4 (output) we (output) ldqm (output) udqm (output) note (output) bank address (output) a10 (output) a0 to a9 (output) d0 to d15 (i/o) off-page note addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 5 memory access control function 136 user's manual u14980ej2v1ud figure 5-9. sdram single read cycle (2/3) (b) during off-page access (whe n latency = 2, page change) tprec pre act rd tw tact tread tlate tlate data address address address address bank address bank address address address row address column address row address row address sdclk (output) sdcke (output) h command sdras (output) sdcas (output) cs3, cs4 (output) we (output) ldqm (output) udqm (output) note (output) bank address (output) a10 (output) a0 to a9 (output) d0 to d15 (i/o) off-page address note addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 5 memory access control function 137 user's manual u14980ej2v1ud figure 5-9. sdram single read cycle (3/3) (c) during on-page access (when latency = 2) rd tw tread tlate tlate data address address column address address address sdclk (output) sdcke (output) h command sdras (output) h sdcas (output) cs3, cs4 (output) we (output) ldqm (output) udqm (output) note (output) bank address (output) a10 (output) a0 to a9 (output) d0 to d15 (i/o) on-page note addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. the timing chart shown here is the timing w hen the previous cycle accessed another cs space or when the bus was in an idle stat e. if access to the same cs space continues, a tw state is not inserted.
chapter 5 memory access control function 138 user's manual u14980ej2v1ud (2) sdram single write cycle the sdram single write cycle is a cycle for writing to sdram by executi ng a write instruction (st) for the sdram area or by 2-cycle dma transfer. in the sdram single write cycle, the active co mmand (act) and write command (wr) are issued for sdram in that order. during on-page access, however , only the write command is issued and the precharge command and active command are not issued. when a page change occurs in the same bank, the precharge command (pre) is issued before the active command. a one-state tw cycle is always inserted immediately bef ore the all read command, which is activated by the cpu. the timing charts of the sdram single write cycle are shown below.
chapter 5 memory access control function 139 user's manual u14980ej2v1ud figure 5-10. sdram single write cycle (1/3) (a) during off-page access tact off-page act wr tw twr twpre twe data address address sdclk (output) sdcke (output) h command sdras (output) sdcas (output) cs3, cs4 (output) we (output) ldqm (output) udqm (output) note (output) address bank address bank address (output) address row address a10 (output) address column address row address a0 to a9 (output) d0 to d15 (i/o) address address note addresses other than the bank address, a10, and a0 to a9. remark the broken lines indicate the high-impedance state.
chapter 5 memory access control function 140 user's manual u14980ej2v1ud figure 5-10. sdram single write cycle (2/3) (b) during off-page access (page change) tprec pre act wr tw tact twr1 twr2 twr3 data address address column address row address aaddress address bank address address bank address address row address off-page sdclk (output) sdcke (output) h command sdras (output) sdcas (output) cs3, cs4 (output) we (output) ldqm (output) udqm (output) note (output) bank address (output) a10 (output) a0 to a9 (output) d0 to d15 (i/o) address row address note addresses other than the bank address, a10, and a0 to a9. remark the broken lines indicate the high-impedance state.
chapter 5 memory access control function 141 user's manual u14980ej2v1ud figure 5-10. sdram single write cycle (3/3) (c) during on-page access wr tw twr twe twpre data on-page sdclk (output) sdcke (output) h command sdras (output) h sdcas (output) cs3, cs4 (output) we (output) ldqm (output) udqm (output) address address note (output) column address a0 to a9 (output) a10 (output) address address bank address (output) d0 to d15 (i/o) note addresses other than the bank address, a10, and a0 to a9. remarks 1. the broken lines indicate the high-impedance state. 2. the timing chart shown here is the timing w hen the previous cycle accessed another cs space or when the bus is an idle state. if access to the same cs space continues, a tw state is not inserted.
chapter 5 memory access control function 142 user's manual u14980ej2v1ud (3) sdram access timing control the sdram access timing can be controlled by sdram configuration registers 3 and 4 (scr3, scr4). for details, refer to 5.3.4 sdram configuration registers 3, 4 (scr3, scr4) . caution wait control by the wait pi n is not available during sdram access. (a) number of waits from bank active command to read/write command the number of wait states from bank active comm and issue to read/write command issue can be set by setting the bcw1n and bcw0n bits of the scrn register (n = 3, 4). bcw1n, bcw0n = 01b: 1 wait bcw1n, bcw0n = 10b: 2 waits bcw1n, bcw0n = 11b: 3 waits (b) number of waits from precharge command to bank active command the number of wait states from precharge command issue to bank active command issue can be set by setting the bcw1n and bcw0n bits of the scrn register (n = 3, 4). bcw1n, bcw0n = 01b: 1 wait bcw1n, bcw0n = 10b: 2 waits bcw1n, bcw0n = 11b: 3 waits (c) cas latency setting when read the cas latency during a read operation can be set by setting the ltm2n to lt m0n bits of the scrn register (n = 3, 4). ltm2n to ltm0n = 010b: latency = 2 ltm2n to ltm0n = 011b: latency = 3 (d) number of waits from refresh command to next command the number of wait states from refresh command i ssue to next command issue can be set by setting the bcw1n and bcw0n bits of the scrn register. the num ber of wait states becom es four times the value set by the bcw1n and bcw0n (n = 3, 4). bcw1n, bcw0n = 01b: 4 waits bcw1n, bcw0n = 10b: 8 waits bcw1n, bcw0n = 11b: 12 waits
chapter 5 memory access control function 143 user's manual u14980ej2v1ud figure 5-11. sdram access timing (1/4) (a) read timing (16-bit bus width word a ccess, page change, bcw = 2, latency = 2) data data data data tw tbcw tact tbcw tread tact tlate tread tlate tread tread tlate tlate tbcw tw tprec add. add. add. bnk. add. bnk. add. bnk. row add. col. col. col. add. row add. sdclk (output) note (output) a11 (output) a0 to a10 (output) bank address (output) sdras (output) sdcas (output) cs3, cs4 (output) rd (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d15 (i/o) h bcw bcw bcw bank a read command bank a read command bank a read command (on-page) bank a read command (on-page) bank a precharge command (page change) bank a active command bank a active command add. add. add. row add. add. row add. add. col. note addresses other than the bank address, a11, and a0 to a10. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. add.: address bnk.: bank address col.: column address row: row address
chapter 5 memory access control function 144 user's manual u14980ej2v1ud figure 5-11. sdram access timing (2/4) (b) read timing (8-bit bus width word access, page cha nge, bcw = 2, latency = 2) data data data data data data data data ta tw tact tbcw tread tread tread tread tbcw tlate tlate tact tbcw tread tread tread tread tlate tlate tprec bcw bcw bcw add. add. row col. col. add. col. col. col. col. col. col. add. row add. add. add. add. add. add. add. add. add. add. sdclk (output) note (output) a10 (output) a0 to a9 (output) bank address (output) sdras (output) sdcas (output) cs3, cs4 (output) rd (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d7 (i/o) h bank a read command bank a read command bank a read command bank a read command bank a read command bank a read command bank a read command bank a read command (on-page) bank a precharge command bank a active command bank a active command (on-page) (page change) add. bnk. add. add. add. row bnk. bnk. add. add. row note addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. add.: address bnk.: bank address col.: column address row: row address
chapter 5 memory access control function 145 user's manual u14980ej2v1ud figure 5-11. sdram access timing (3/4) (c) write timing (16-bit bus width word a ccess, bank change, bcw = 1, latency = 2) sdclk (output) note (output) a11 (output) a0 to a10 (output) bank address (output) sdras (output) sdcas (output) cs3, cs4 (output) rd (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d15 (i/o) add. add. add. add. add. add. add. add. add. col. add. row col. row col. col. col. col. data data data data h tw tact twr twr twpre bcw bank a write twe tact tw twr twr bcw bank b write twpre twe tw tw twe twr twr twpre bank b write bank a write command bank a write command bank b write command bank a active command bank b active command bank b write command bank b write command bank b write command bank a precharge command add. bnk. add. bnk. bnk. add. add. add. add. add. add. row add. row add. data data when of write-accessing the page that includes bank b, which was accessed by the previous write access. note addresses other than the bank address, a11, and a0 to a10. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. add.: address bnk.: bank address col.: column address row: row address
chapter 5 memory access control function 146 user's manual u14980ej2v1ud figure 5-11. sdram access timing (4/4) (d) write timing (8-bit bus width word access, bank cha nge, bcw = 1, latency = 2) sdclk (output) note (output) a10 (output) a0 to a9 (output) bank address (output) sdras (output) sdcas (output) cs3, cs4 (output) rd (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d7 (i/o) add. add. add. add. add. add. add. add. add. add. add. add. add. add. add. add. add. add. add. bnk. col. col. col. col. bnk. data data data data data data data data h data data data tw tact twr twr twr twr bcw bank a write twpre twe tw tact tw tact twr twr twr twr bcw bcw twpre twe tread tread tread tread tlate tlate bank b write bank a read bank a active command bank a write command bank a write command bank a write command bank a write command bank a precharge command bank b active command bank b write command bank b write command bank b write command bank b write command bank b precharge command bank a active command bank a read command bank a read command bank a read command bank a read command add. bnk. add. bnk. bnk. add. add. add. add. add. add. row add. row col. col. col. col. add. row col. col. col. col. add. row row add. add. row data note addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. add.: address bnk.: bank address col.: column address row: row address
chapter 5 memory access control function 147 user's manual u14980ej2v1ud 5.3.6 refresh control function the v850e/ma2 can generate a refresh cycle. the refresh c ycle is set with sdram refresh control registers 3 and 4 (rfs3, rfs4). the rfs3 and rfs4 registers correspond to cs3 and cs4. for example, to connect sdram to cs3, set rfs3. when another bus master occupies the ex ternal bus, the sdram controller can not occupy the external bus. in this case, the sdram controller issues a refresh request to the bus master by changing the refrq signal to active (low level). during a refresh operation, the address bus retains t he state it was in just before the refresh cycle. (1) sdram refresh control registers 3, 4 (rfs3, rfs4) these registers are used to enable or disable a refresh and set the refresh interval. the refresh interval is determined by the following calculation formula. refresh interval ( s) = refresh count clock (t rcy ) interval factor the refresh count clock and interval factor are determined by the renn bit and rin5n to rin0n bits, respectively, of the rfsn register. note that n corresponds to the register number (3 , 4) of sdram configuration registers 3 and 4 (scr3, scr4). these registers can be read/written in 16-bit units. cautions 1. write to the rfs3 and rfs4 registers after reset, and then do not change the set value. also, do not access an external memory area ot her than the one for this initialization routine until the initial setting of the rfs3 and rfs4 registers is complete. however, it is possible to access external memory areas whose initialization settings are complete. 2. immediately after the renn bit of the rfsn register is set (1), the refresh cycle may be executed for the sdram (n = 3, 4). this do es not affect the refresh cycle occurring at this time nor the operations after the refr esh cycle is executed. the refresh cycles occurring thereafter will be execu ted normally according to th e set interval. however, set the rfsn register as shown below for applications which will have problems with this refresh cycle. <1> with the mea bit of the bctm register set (1), set the bta1 and bta0 bits to 01 (page rom connection) (m = 0, 1, a: a = 3 when m = 0, a = 4 when m = 1). <2> set the renn bit of the rfsn regi ster (1) to enable refresh (n = 3, 4). <3> with the mea bit of the bctm register set (1), set the bta1 and bta0 bits to 11 (sdram connection) (m = 0, 1, a: a = 3 when m = 0, a = 4 when m = 1). <4> set the scrn register to initialize the sdram (n = 3, 4).
chapter 5 memory access control function 148 user's manual u14980ej2v1ud 15 address fffff4aeh after reset 0000h 14131211109876543210 ren3 rfs3 0 0 0 0 0 rcc13 rcc03 00 rin53 rin43 rin33 rin23 rin13 rin03 ren4 rfs4 fffff4b2h 0000h 00000 rcc14 rcc04 00 rin54 rin44 rin34 rin24 rin14 rin04 bit position bit name function 15 ren3, ren4 refresh enable specifies whether cbr refresh is enabled or disabled. 0: refresh disabled 1: refresh enabled refresh count clock specifies the refresh count clock (t rcy ). rcc1n rcc0n refresh count clock (t rcy ) 0 0 32/f xx 0 1 128/f xx 1 0 256/f xx 1 1 setting prohibited 9, 8 rcc1n, rcc0n (n = 3, 4) refresh interval sets the interval factor of the interval timer for the generation of the refresh timing. rin5n rin4n rin3n rin2n rin1n rin0n interval factor 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : : : : : : 1 1 1 1 1 1 64 5 to 0 rin5n to rin0n (n = 3, 4) remark f xx : internal system clock
chapter 5 memory access control function 149 user's manual u14980ej2v1ud table 5-1. example of interval factor settings interval factor value notes 1, 2 specified refresh interval value ( s) refresh count clock (t rcy ) f xx = 20 mhz f xx = 33 mhz f xx = 40 mhz 32/f xx 9 (14.4) 16 (15.5) 19 (15.2) 128/f xx 2 (12.8) 4 (15.5) 4 (12.8) 15.6 256/f xx 1 (12.8) 2 (15.5) 2 (12.8) notes 1. the interval factor is set by bits rin0n to rin5n of the rfsn register (n = 3, 4). 2. the values in parentheses are the calc ulated values for the refresh interval ( s). refresh interval ( s) = refresh count clock (t rcy ) interval factor remark f xx : internal system clock the v850e/ma2 can automatica lly generate an auto refresh cycle and a self refresh cycle.
chapter 5 memory access control function 150 user's manual u14980ej2v1ud (2) auto refresh cycle in the auto refresh cycle, the auto refresh command (ref ) is issued four clocks after the precharge command for all banks (pall) is issued. figure 5-12. auto refresh cycle trefw pall ref tabpw trefw trefw tref h h address auto-refresh cycle sdclk (output) sdcke (output) h command sdras (output) sdcas (output) cs3, cs4 (output) we (output) ldqm (output) udqm (output) address (output) a10 (output) d0 to d15 (i/o) remark the broken lines indicate the high-impedance state.
chapter 5 memory access control function 151 user's manual u14980ej2v1ud (3) refresh timing figure 5-13. cbr refresh timing (sdram) d0 to d15 (i/o) we (output) rd (output) sdcas (output) sdras (output) cs3, cs4 (output) a0 to a9, a11 to a23 (output) a10 (output) sdclk (output) allpre tw tw tref tbcw tbcw tw tbcw tbcw tbcw tbcw tbcw tbcw ti ti sdcke (output) ldqm (output) udqm (output) all-bank precharge command refresh command (1st) h h h bcw 4clk remarks 1. the number of wait states set by the bc w1n and bcw0n bits of the scrn register 4 clocks will be inserted in bcw 4 clk period. 2. the broken lines indicate the high-impedance state.
chapter 5 memory access control function 152 user's manual u14980ej2v1ud 5.3.7 self-refresh control function in the case of transition to the idle mode or software stop mode, the sdram controller generates the cbr self- refresh cycle. note that the sdras pulse width of sdram must meet the specification for sdram to enter the self-refresh operation. caution the internal rom and internal ram can be accessed even in the self-refr esh cycle. however, access to an on-chip peripheral i/o register or external device is held pending until the self- refresh cycle is cleared. to release the self-refresh cycle, follow either of the three methods below. (1) release by nmi input (a) in the case of self-refresh cycle in idle mode to release the self-refresh cycle, make the s dras, sdcas, ldqm, and udqm signals inactive immediately. (b) in the case of self-refresh cycle in software stop mode to release the self-refresh cycle, make the sdr as, sdcas, ldqm, and udqm signals inactive after stabilizing oscillation. (2) release by intp0n0 and intp0n1 inputs (n = 0, 1) (a) in the case of self-refresh cycle in idle mode to release the self-refresh cycle, make the s dras, sdcas, ldqm, and udqm signals inactive immediately. (b) in the case of self-refresh cycle in software stop mode to release the self-refresh cycle, make the sdr as, sdcas, ldqm, and udqm signals inactive after stabilizing oscillation. (3) release by reset input
chapter 5 memory access control function 153 user's manual u14980ej2v1ud figure 5-14. self refresh timing (sdram) d0 to d15 (i/o) we (output) rd (output) sdcas (output) sdras (output) cs3, cs4 (output) a0 to a9, a11 to a23 (output) a10 (output) note sdclk (output) tw tw nop tw tref tw tw ti ti tw tw tdcw tdcw tdcw tdcw sdcke (output) ldqm (output) udqm (output) all-bank precharge command refresh command nop command h h bcw 4clk note shown above is the case when the self-refresh cycle is started in the idle or software stop mode. remarks 1. the number of wait states set by the bc w1n and bcw0n bits of the scrn register 4 clocks will be inserted in bcw 4 clk period (n = 3, 4). 2. the broken lines indicate the high-impedance state.
chapter 5 memory access control function 154 user's manual u14980ej2v1ud 5.3.8 sdram initialization sequence be sure to initialize sdram when applying power. (1) set the registers of sdram (other than sdra m configuration registers 3 and 4 (scr3, scr4)) ? bus cycle type configuration r egisters 0 and 1 (bct0, bct1) ? bus cycle control register (bcc) ? sdram refresh control registers 3 and 4 (rfs3, rfs4) (2) set sdram configuration registers 3 and 4 (scr3, scr4). when writing data to these registers, the following commands are issued for sdram in the order shown. ? all bank precharge command ? refresh command (8 times) ? command that is used to set a mode register figures 5-15 and 5-16 show examples of sdram mode register setting timing. caution when using the sdclk and sdcke signals, it is necessary to set the sdlck output mode and the sdcke output mode for these signals by setting the pmccd register. in this case, however, these settings must not be executed at the same time. be sure to set the sdcke output mode a fter setting the sdclk output mode (refer to 13.3.12 (2) (b) port cd mode control register (pmccd)).
chapter 5 memory access control function 155 user's manual u14980ej2v1ud figure 5-15. sdram mode register setting cycle trefw pall ref mrs tabpw trefw trefw tref md md h h mode register setting cycle refresh command (ref) (generated 8 times) sdclk (output) sdcke (output) h command sdras (output) sdcas (output) cs3, cs4 (output) we (output) ldqm (output) udqm (output) address (output) a10 (output) d0 to d15 (i/o) remark the broken lines indicate the high-impedance state.
chapter 5 memory access control function 156 user's manual u14980ej2v1ud figure 5-16. sdram register write operation timing alpre tw tw tw tref tw tw tref tw tw tw regw tw tw tw tw tw tw d0 to d15 (i/o) we (output) rd (output) sdcas (output) sdras (output) cs3, cs4 (output) a0 to a9 (output) a10 (output) bank address (output) note (output) sdclk (output) sdcke (output) h ldqm (output) udqm (output) scrn register write all-bank precharge command refresh command (1st time) register write command refresh command (2nd time) refresh end (1st time) refresh end (8th time) sdram access enabled refresh (7 times) note addresses other than the bank address, a10, and a0 to a9. remark the broken lines indicate the high-impedance state.
157 user's manual u14980ej2v1ud chapter 6 dma functions (dma controller) the v850e/ma2 includes a direct memory access (dma) controller (dmac) that ex ecutes and controls dma transfer. the dmac controls data transfer between memory and i/o, or among memories, based on dma requests issued by the on-chip peripheral i/o (serial in terface, real-time pulse unit, and a/d converter), dmarq0 and dmarq1 pins, or software triggers (memory refers to internal ram or external memory). 6.1 features ? 4 independent dma channels transfer units: 8/16 bits maximum transfer count: 65,536 (2 16 ) two-cycle transfer three transfer modes single transfer mode single-step transfer mode block transfer mode transfer requests request by interrupts from on-chip peripheral i/o (s erial interface, real-time pulse unit, a/d converter) requests by dmarq0, dmarq1 pin input requests by software trigger transfer objects memory ? i/o memory ? memory dma transfer end output signals (tc0) next address setting function
chapter 6 dma functions (dma controller) 158 user's manual u14980ej2v1ud 6.2 configuration tc0 cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850e/ma2 bus interface external bus external ram external rom external i/o dma source address register (dsanh/dsanl) dma transfer count register (dbcn) dma channel control register (dchcn) dma terminal count output control register (dtoc) dma destination address register (ddanh/ddanl) dmarqx dmaakx dma addressing control register (dadcn) dma disable status register (ddis) dma trigger factor register (dtfrn) dma restart register (drst) remark n = 0 to 3, x = 0, 1
chapter 6 dma functions (dma controller) 159 user's manual u14980ej2v1ud 6.3 control registers 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) these registers are used to set the dma source addresses (28 bits each) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, dsanh and dsanl. since these registers are configured as 2-stage fifo buffe r registers, a new source address for dma transfer can be specified during dma transfer. (refer to 6.9 next address setting function .) (1) dma source address registers 0h to 3h (dsa0h to dsa3h) these registers can be read/written in 16-bit units. be sure to set bits 14 to 12 to 0. if they are set to 1, the operation is not guaranteed. caution when setting an address of a peripheral i/o register for th e source address, be sure to specify an address between ffff000h and fffff ffh. an address of the peripheral i/o register image (3fff000h to 3 ffffffh) must not be specified. 15 ir dsa0h address fffff082h after reset undefined 14 0 13 0 12 0 11 sa27 10 sa26 9 sa25 8 sa24 7 sa23 6 sa22 5 sa21 4 sa20 3 sa19 2 sa18 1 sa17 0 sa16 ir dsa1h fffff08ah undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 ir dsa2h fffff092h undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 ir dsa3h fffff09ah undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 bit position bit name function 15 ir internal ram select specifies the dma source address. 0: external memory, on-chip peripheral i/o 1: internal ram 11 to 0 sa27 to sa16 source address sets the dma source addresses (a27 to a16). during dma transfer, it stores the next dma transfer source address.
chapter 6 dma functions (dma controller) 160 user's manual u14980ej2v1ud (2) dma source address registers 0l to 3l (dsa0l to dsa3l) these registers can be read/written in 16-bit units. 15 sa15 dsa0l address fffff080h after reset undefined 14 sa14 13 sa13 12 sa12 11 sa11 10 sa10 9 sa9 8 sa8 7 sa7 6 sa6 5 sa5 4 sa4 3 sa3 2 sa2 1 sa1 0 sa0 sa15 dsa1l fffff088h undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa15 dsa2l fffff090h undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa15 dsa3l fffff098h undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 bit position bit name function 15 to 0 sa15 to sa0 source address sets the dma source address (a15 to a0). during dma transfer, it stores the next dma transfer source address.
chapter 6 dma functions (dma controller) 161 user's manual u14980ej2v1ud 6.3.2 dma destination address regi sters 0 to 3 (dda0 to dda3) these registers are used to set the dma destination address (28 bits each) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, ddanh and ddanl. since these registers are configured as 2-stage fifo buffer registers, a ne w destination address for dma transfer can be specified during dma transfer. (refer to 6.9 next address setting function .) (1) dma destination address register s 0h to 3h (dda0h to dda3h) these registers can be read/written in 16-bit units. be sure to set bits 14 to 12 to 0. if they are set to 1, the operation is not guaranteed. caution when setting an address of a peripheral i/o re gister for the destination address, be sure to specify an address between ffff000h and fffff ffh. an address of the peripheral i/o register image (3fff000h to 3 ffffffh) must not be specified. 15 ir dda0h address fffff086h after reset undefined 14 0 13 0 12 0 11 da27 10 da26 9 da25 8 da24 7 da23 6 da22 5 da21 4 da20 3 da19 2 da18 1 da17 0 da16 ir dda1h fffff08eh undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 ir dda2h fffff096h undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 ir dda3h fffff09eh undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 bit position bit name function 15 ir internal ram select specifies the dma destination address. 0: external memory, on-chip peripheral i/o 1: internal ram 11 to 0 da27 to da16 destination address sets the dma destination addresses (a27 to a16). during dma transfer, it stores the next dma transfer destination address.
chapter 6 dma functions (dma controller) 162 user's manual u14980ej2v1ud (2) dma destination address regist ers 0l to 3l (dda0l to dda3l) these registers can be read/written in 16-bit units. 15 da15 dda0l address fffff084h after reset undefined 14 da14 13 da13 12 da12 11 da11 10 da10 9 da9 8 da8 7 da7 6 da6 5 da5 4 da4 3 da3 2 da2 1 da1 0 da0 da15 dda1l fffff08ch undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 da15 dda2l fffff094h undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 da15 dda3l fffff09ch undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 bit position bit name function 15 to 0 da15 to da0 destination address sets the dma destination address (a15 to a0). during dma transfer, it stores the next dma transfer destination address.
chapter 6 dma functions (dma controller) 163 user's manual u14980ej2v1ud 6.3.3 dma byte count registers 0 to 3 (dbc0 to dbc3) these 16-bit registers are used to set the byte transfer counts for dma channels n (n = 0 to 3). they store the remaining transfer counts during dma transfer. since these registers are configured as 2-stage fifo buffer registers, a new dma byte transfer count for dma transfer can be specified during dma transfer. (refer to 6.9 next address setting function .) these registers are decremented by 1 for each tr ansfer, and transfer ends when a borrow occurs. these registers can be read/written in 16-bit units. remark if a terminal count occurs without the dbcn regist er being rewritten during dma transfer and then the dbcn register is read, the value set immediatel y before the dma transfer is read (even after the completion of transfer, 0000h is not read). 15 bc15 dbc0 address fffff0c0h after reset undefined 14 bc14 13 bc13 12 bc12 11 bc11 10 bc10 9 bc9 8 bc8 7 bc7 6 bc6 5 bc5 4 bc4 3 bc3 2 bc2 1 bc1 0 bc0 bc15 dbc1 fffff0c2h undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bc15 dbc2 fffff0c4h undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bc15 dbc3 fffff0c6h undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bit position bit name function byte count sets the byte transfer count. it stores t he remaining byte transfer count during dma transfer. dbcn (n = 0 to 3) states 0000h byte transfer count 1 or remaining byte transfer count 0001h byte transfer count 2 or remaining byte transfer count : : ffffh byte transfer count 65,536 (2 16 ) or remaining byte transfer count 15 to 0 bc15 to bc0
chapter 6 dma functions (dma controller) 164 user's manual u14980ej2v1ud 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) these 16-bit registers are used to control the dma transfer modes for dma channel n (n = 0 to 3). these registers cannot be accessed during dma operation. they can be read/written in 16-bit units. be sure to set bits 13 to 8, 1, and 0 to 0. if they are set to 1, the operation is not guaranteed. caution the ds1 and ds0 bits are used to set how many bits of da ta are transferred. when 8-bit data (ds1, ds0 bits = 00) is set, th e lower data bus (d0 to d7 ) is not necessarily used. when the transfer data size is set to 16 bits, th e transfer must start from an address with bit 1 of the lower address aligned to "0". in this case, the transfer cannot start from an odd address. (1/2) 15 ds1 dadc0 address fffff0d0h after reset 0000h 14 ds0 13 0 12 0 11 0 10 0 9 0 8 0 7 sad1 6 sad0 5 dad1 4 dad0 3 tm1 2 tm0 1 0 0 0 ds1 dadc1 fffff0d2h 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 00 ds1 dadc2 fffff0d4h 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 00 ds1 dadc3 fffff0d6h 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 00 bit position bit name function data size sets the transfer data size for dma transfer. ds1 ds0 transfer data size 0 0 8 bits 0 1 16 bits 1 0 setting prohibited 1 1 setting prohibited 15, 14 ds1, ds0 source address count direction sets the count direction of the source address for dma channel n (n = 0 to 3). sad1 sad0 count direction 0 0 increment 0 1 decrement 1 0 fixed 1 1 setting prohibited 7, 6 sad1, sad0
chapter 6 dma functions (dma controller) 165 user's manual u14980ej2v1ud (2/2) bit position bit name function destination address count direction sets the count direction of the destinat ion address for dma channel n (n = 0 to 3). dad1 dad0 count direction 0 0 increment 0 1 decrement 1 0 fixed 1 1 setting prohibited 5, 4 dad1, dad0 transfer mode sets the transfer mode during dma transfer. tm1 tm0 transfer mode 0 0 single transfer mode 0 1 single-step transfer mode 1 0 setting prohibited 1 1 block transfer mode 3, 2 tm1, tm0
chapter 6 dma functions (dma controller) 166 user's manual u14980ej2v1ud 6.3.5 dma channel control regist ers 0 to 3 (dchc0 to dchc3) these 8-bit registers are used to c ontrol the dma transfer operating mode for dma channel n (n = 0 to 3). these registers can be read/written in 8-bit or 1-bit units . (however, bit 7 is read only and bits 2 and 1 are write only. if bits 2 and 1 are read, the read value is always 0.) be sure to set bits 6 to 4 to 0. if they are set to 1, the operation is not guaranteed. caution setting the mlen bit to 1 is valid only for starting dma transfer (hardware dma) by dmarqm pin input or an interrupt from the on- chip peripheral i/o (n = 0 to 3, m = 0, 1). to start dma transfer (software dma) by setting the stgn bit to 1, read the tcn bit and check that it is set to 1, and then set the stgn bit to 1. (1/2) address fffff0e0h <7> tc0 dchc0 6 0 5 0 4 0 <3> mle0 <2> init0 <1> stg0 <0> e00 after reset 00h fffff0e2h tc1 dchc1 0 0 0 mle1 init1 stg1 e11 00h fffff0e4h tc2 dchc2 0 0 0 mle2 init2 stg2 e22 00h fffff0e6h tc3 dchc3 0 0 0 mle3 init3 stg3 e33 00h bit position bit name function 7 tcn terminal count this status bit indicates whether dma tran sfer through dma channel n has ended or not. this bit is read-only. it is set to 1 when dm a transfer ends and cleared (to 0) when it is read. 0: dma transfer had not ended. 1: dma transfer had ended. 3 mlen multi link enable bit when this bit is set to 1 at terminal count output, the enn bit is not cleared to 0 and the dma transfer enable state is retained. when the next dma transfer request is a dmar qm pin input or an interrupt from the on- chip peripheral i/o (hardware dma), the dm a transfer request can be acknowledged even when the tcn bit is not read. when the next dma transfer request is the sett ing of the stgn bit to 1 (software dma), the dma transfer request can be acknowledged by reading and clearing the tcn bit to 0. when this bit is cleared to 0 at terminal c ount output, the enn bit is cleared to 0 and the dma transfer disable state is entered. at the next dma transfer request, the setting of the enn bit to 1 and the reading of the tcn bit are required. 2 initn initialize when this bit is set to 1, dma tr ansfer is forcibly terminated. remark n = 0 to 3 n = 0, 1
chapter 6 dma functions (dma controller) 167 user's manual u14980ej2v1ud (2/2) bit position bit name function 1 stgn software trigger if this bit is set to 1 in the dma transfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. 0 enn enable specifies whether dma transfer through dma chan nel n is to be enabled or disabled. this bit is cleared to 0 when dma transfer ends. it is also cleared to 0 when dma transfer is forcibly terminated by means of setting the initn bit to 1 or by nmi input. 0: dma transfer disabled 1: dma transfer enabled remark n = 0 to 3 m = 0, 1
chapter 6 dma functions (dma controller) 168 user's manual u14980ej2v1ud 6.3.6 dma disable status register (ddis) this register holds the contents of the enn bit of the dchcn register during nmi input (n = 0 to 3). this register is read-only in 8-bit units. be sure to set bits 7 to 4 to 0. if they are set to 1, the operation is not guaranteed. address fffff0f0h 7 0 ddis 6 0 5 0 4 0 3 ch3 2 ch2 1 ch1 0 ch0 after reset 00h bit position bit name function 3 to 0 ch3 to ch0 nmi interrupt status reflects the contents of the enn bit of the dchcn register during nmi input. the contents of this register are held until the next nmi input or until the system is reset. 6.3.7 dma restart register (drst) this register is used to restart dma transfer that has been forcibly interrupt ed by nmi input. the enn bit of this register and the enn bit of the dchcn register are linked to each other (n = 0 to 3). following forcible interrupt by nmi input, the dma channel that was interrupted is conf irmed from the contents of the ddis register, and dma transfer is restarted by setting the enn bit of the corresponding channel to 1. this register can be read/written in 8-bit units. be sure to set bits 7 to 4 to 0. if they are set to 1, the operation is not guaranteed. address fffff0f2h 7 0 drst 6 0 5 0 4 0 3 en3 2 en2 1 en1 0 en0 after reset 00h bit position bit name function 3 to 0 en3 to en0 restart enble specifies whether dma transfer through dma channel n is to be enabled or disabled. this bit is cleared to 0 when dma transfer is completed in accordance with the terminal count output (n = 0 to 3). it is also cleared to 0 when dma transfer is fo rcibly terminated by setting the initn bit of the dchcn register to 1 or by nmi input. 0: dma transfer disabled 1: dma transfer enabled
chapter 6 dma functions (dma controller) 169 user's manual u14980ej2v1ud 6.3.8 dma terminal count output control register (dtoc) the dma terminal count output control regi ster (dtoc) is an 8-bit register that controls the terminal count outputs from each dma channel. terminal count signals from each dma channel can be brought together and output from the tc0 pin. this register can be read/written in 8-bit or 1-bit units. address fffff8a0h 7 0 dtoc 6 0 5 0 4 0 <3> tco3 <2> tco2 <1> tco1 <0> tco0 after reset 01h bit position bit name function 3 to 0 tco3 to tco0 terminal count output indicates the state of the tc0 pin. 0: channel n?s terminal count si gnal not output from tc0 pin. 1: channel n?s terminal count signal output from tc0 pin. the following shows an example of the case when the dtoc register is set to 03h. tc0 (output) dma0 cpu dma0 dma1 dma1 cpu dma2 dma2 dma channel 2 terminal count dma channel 1 terminal count dma channel 0 terminal count
chapter 6 dma functions (dma controller) 170 user's manual u14980ej2v1ud 6.3.9 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) these 8-bit registers are used to control the dma transfe r start trigger through interrupt requests from on-chip peripheral i/o. the interrupt requests set with these register s serve as dma transfer startup factors. these registers can be read/written in 8-bit units. howe ver, only bit 7 (dfn) can be read/written in 1-bit units. cautions 1. when changing the se tting of the dtfrn register, be sure to stop the dma operation. 2. an interrupt request input in the standby mode (idle or software stop mode) cannot be a dma transfer start factor. (1/2) address fffff810h <7> df0 dtfr0 6 0 5 ifc05 4 ifc04 3 ifc03 2 ifc02 1 ifc01 0 ifc00 after reset 00h fffff812h df1 dtfr1 0 ifc15 ifc14 ifc13 ifc12 ifc11 ifc10 00h fffff814h df2 dtfr2 0 ifc25 ifc24 ifc23 ifc22 ifc21 ifc20 00h fffff816h df3 dtfr3 0 ifc35 ifc34 ifc33 ifc32 ifc31 ifc30 00h bit position bit name function 7 dfn dma request flag this is a dma transfer request flag. only 0 can be written to this flag. 0: dma transfer not requested 1: dma transfer requested if the interrupt specified as the dma transfer st artup factor occurs and it is necessary to clear the dma transfer request while dma trans fer is disabled (including when it is aborted by nmi or forcibly terminated by software) , stop the operation of the source causing the interrupt, and then clear the dfn bit to 0 (for example, disable reception in the case of serial reception). if it is clear that t he interrupt does not occur until dma transfer is resumed next, it is not necessary to stop the operation of the source causing the interrupt. interrupt factor code this code is used to set the interrupt source s serving as dma transfer startup factors. ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request from on-chip peripheral i/o disabled 0 0 0 0 0 1 intp000/intm000 0 0 0 0 1 0 intp001/intm001 0 0 0 0 1 1 intp010/intm010 0 0 0 1 0 0 intp011/intm011 0 0 1 0 0 1 intp100 0 0 1 0 1 0 intp101 5 to 0 ifcn5 to ifcn0
chapter 6 dma functions (dma controller) 171 user's manual u14980ej2v1ud (2/2) bit position bit name function ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 1 1 0 1 intp110 0 1 1 0 0 1 intcmd0 0 1 1 0 1 0 intcmd1 0 1 1 0 1 1 intcmd2 0 1 1 1 0 0 intcmd3 0 1 1 1 0 1 intcsi0 0 1 1 1 1 0 intsr0 0 1 1 1 1 1 intst0 1 0 0 0 0 0 intcsi1 1 0 0 0 0 1 intsr1 1 0 0 0 1 0 intst1 1 0 0 1 1 0 intad other than above setting prohibited 5 to 0 ifcn5 to ifcn0 remark n = 0 to 3 the relationship between the dmarqn signa l and the interrupt source that serv es as a dma transfer trigger is as follows. dmarqx ifcn0 to ifcn5 internal dma request signal interrupt source selector remark x = 0, 1, n = 0 to 3 remark if an interrupt request is specified as the dma trans fer start factor, an interrupt request will be generated if dma transfer starts. to prevent an interrupt fr om being generated, mask the interrupt by setting the interrupt request control register. dma trans fer starts even if an interrupt is masked.
chapter 6 dma functions (dma controller) 172 user's manual u14980ej2v1ud 6.4 dma bus states 6.4.1 types of bus states the dmac bus states consis t of the following 10 states. (1) ti state the ti state is an idle state, duri ng which no access request is issued. the dmarq0 and dmarq1 signals are sampled at the rising edge of the clkout signal. (2) t0 state dma transfer ready state (state in which a dma transfe r request has been issued and the bus mastership is acquired for the first dma transfer). (3) t1r state the bus enters the t1r state at the beginning of a read operation in the two-cycle transfer mode. address driving starts. after entering the t1r st ate, the bus invariably enters the t2r state. (4) t1ri state the t1ri state is a state in whic h the bus waits for the acknowledge signal corresponding to an external memory read request. after entering the last t1ri state, t he bus invariably enters the t2r state. (5) t2r state the t2r state corresponds to the last state of a read operation in the two-cycle transfer mode, or to a wait state. in the last t2r state, read data is sampled. after entering the last t2r state, the bus invariably enters the t1w state. (6) t2ri state state in which the bus is ready for dma transfer to on-chip peripheral i/o or inte rnal ram (state in which the bus mastership is acquired for dma transfer to on-chip peripheral i/o or internal ram). after entering the last t2ri state, t he bus invariably enters the t1w state. (7) t1w state the bus enters the t1w state at the beginning of a write operatio n in the two-cycle transfer mode. address driving starts. after entering the t1w st ate, the bus invariably enters the t2w state. (8) t1wi state state in which the bus waits for the acknowledge signal corresponding to an external memory write request. after entering the last t1wi state, t he bus invariably enters the t2w state. (9) t2w state the t2w state corresponds to the last state of a write operat ion in the two-cycle transfer mode, or to a wait state. in the last t2w state, the writ e strobe signal is made inactive. (10) te state the te state corresponds to dma transfer completion. va rious internal signals are initialized (n = 0 to 3). after entering the te state, the bus invariably enters the ti state.
chapter 6 dma functions (dma controller) 173 user's manual u14980ej2v1ud 6.4.2 dmac bus cycle state transition except for the block transfer mode, each time the processi ng for a dma transfer is completed, the bus mastership is released. figure 6-1. dmac bus cycle state transition two-cycle transfer ti t0 t1r t1ri t2r t1w t2w te ti t2ri t1wi
chapter 6 dma functions (dma controller) 174 user's manual u14980ej2v1ud 6.5 transfer modes 6.5.1 single transfer mode in single transfer mode, the dmac releases the bus at eac h byte/halfword transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request takes precedence. if another dma transfer requ est with a lower priority occurs within one clock after single transfer has been completed, however, this request does not take precedence even if the previous dma transfer request signal with the higher priority remains ac tive. dma transfer with the newly issued lower priority request is executed after the cpu bus has been released. figures 6-2 to 6-4 show examples of single transfer. figure 6-2. single transfer example 1 cpu dmarq1 (input) cpu dma1 cpu dma1 cpu dma1 cpu cpu cpu cpu cpu cpu dma1 cpu dma1 cpu cpu cpu dma channel 1 terminal count note note note note note the bus is always released. figure 6-3 shows an example of a single transfer in which a higher priority dma request is issued. dma channel 0 is in the block transfer mode and channel 1 is in the single transfer mode. figure 6-3. single transfer example 2 cpu cpu cpu dma1 cpu dma0 dma0 cpu dma1 cpu dma1 cpu dma1 cpu dma1 cpu dma1 dmarq1 (input) dmarq0 (input) dma channel 1 terminal count dma channel 0 terminal count note note note note note note the bus is always released.
chapter 6 dma functions (dma controller) 175 user's manual u14980ej2v1ud figure 6-4 is an example of single transfer where a dma tr ansfer request a lower priority is issued one clock after single transfer has been completed. dma channels 0 and 1 are used for single transfer. if two dma transfer request signals are asserted at the same time, two dma transfer operations are alternately executed. figure 6-4. single transfer example 3 cpu cpu cpu dma0 dma0 cpu dma0 cpu dma0 cpu dma0 cpu cpu cpu dma0 cpu dma1 cpu dma1 dma channel 1 terminal count dma channel 0 terminal count dmarq1 (input) dmarq0 (input) note note note note note note note note the bus is always released.
chapter 6 dma functions (dma controller) 176 user's manual u14980ej2v1ud 6.5.2 single-step transfer mode in single-step transfer mode, the dmac releases the bus at each byte/halfword transfer. if there is a subsequent dma transfer request signal (dmarq0, dmarq1), transfer is performed again. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. the following shows an example of a single-step transfer. figure 6-6 shows an example of single-step transfer made in which a higher priority dma request is issued. dma channels 0 and 1 are in t he single-step transfer mode. figure 6-5. single-step transfer example 1 cpu cpu cpu dma1 cpu dma1 cpu dma1 cpu dma1 cpu cpu cpu cpu cpu cpu cpu dma channel 1 terminal count dmarq1 (input) note note note note the bus is always released. figure 6-6. single-step transfer example 2 cpu cpu cpu dma1 cpu dma1 cpu dma0 cpu dma0 cpu dma0 cpu dma1 cpu dma1 cpu dma channel 0 terminal count dma channel 1 terminal count dmarq1 (input) dmarq0 (input) note note note note note note note the bus is always released.
chapter 6 dma functions (dma controller) 177 user's manual u14980ej2v1ud 6.5.3 block transfer mode in the block transfer mode, once transfer starts, the dm ac continues the transfer oper ation without releasing the bus until a terminal count occurs. no other dma requests are acknowledged during block transfer. after the block transfer ends and the dmac releases the bus, another dma transfer can be acknowledged. the bus cycle of the cpu is not inserted during block transfer, but bus hold and refresh cycles are inserted in between dma transfer operations. the following shows an example of block transfer in which a higher priority dma request is issued. dma channels 0 and 1 are in the block transfer mode. figure 6-7. block transfer example cpu cpu cpu dma1 dma1 dma1 dma1 dma1 dma1 dma1 dma1 cpu dma0 dma0 dma0 dma0 dma0 dma channel 1 terminal count the bus is always released. dmarq1 (input) dmarq0 (input)
chapter 6 dma functions (dma controller) 178 user's manual u14980ej2v1ud 6.6 two-cycle transfer in two-cycle transfer, data transfer is performed in two cy cles, a read cycle (source to dmac) and a write cycle (dmac to destination). in the first cycle, the source address is output and readin g is performed from the source to the dmac. in the second cycle, the destination address is output and writi ng is performed from the dmac to the destination. caution an idle cycle of 1 cl ock is always inserted between the read cycle and write cycle.
chapter 6 dma functions (dma controller) 179 user's manual u14980ej2v1ud figure 6-8. timing of access to sram, external rom, and external i/o during 2-cycle dma transfer (1/2) (a) sram external i/o (bcc register setting for sram: bcn1, bcn0 = 00b) (bcc register setting for external i/o: bcn1, bcn0 = 00b) t1 t2 ti note t2 t1 a0 to a24 (output) d0 to d15 (i/o) dmarqx (input) clkout (output) csn (output) of sram area csn (output) of external i/o area rd (output) wait (input) we (output) dmaakx (output) tc0 (output) lbe (output) ube (output) lwr (output) uwr (output) address address data data note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7, x = 0, 1
chapter 6 dma functions (dma controller) 180 user's manual u14980ej2v1ud figure 6-8. timing of access to sram, external rom, and external i/o during 2-cycle dma transfer (2/2) (b) sram external i/o (bcc register se tting for sram: bcn1, bcn0 = 11b) (bcc register setting for external i/o: bcn1, bcn0 = 00b) t1 t2 a0 to a24 (output) d0 to d15 (i/o) dmarqx (input) clkout (output) csn (output) of sram area csn (output) of external i/o area rd (output) wait (input) we (output) dmaakx (output) tc0 (output) lbe (output) ube (output) lwr (output) uwr (output) ti note 2 ti note 1 ti note 1 ti note 1 t1 t2 address address data data notes 1. this idle state (ti) is inserted by means of a bcc register setting. 2. this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7, x = 0, 1
chapter 6 dma functions (dma controller) 181 user's manual u14980ej2v1ud figure 6-9. timing of 2-cycl e dma transfer (external i/o sram) (a) single-step transfer mode ti ti ti ti ti note to t1r t1 t2r t2 t1w t1 t2w t2 t1r t1 t2r tw t2r t2 ti note t2w tw t1w t1 t2w t2 ti ti ti to csn (output) of sram area d0 to d15 (i/o) a0 to a24 (output) internal dma request signal dmarqx (input) clkout (output) tc0 (output) csm (output) of external i/o area rd (output) wait (input) we (output) data data h dmaakx (output) lwr (output) uwr (output) address address address address data data note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7, m = 0, 3, 4, 7 (n m), x = 0, 1
chapter 6 dma functions (dma controller) 182 user's manual u14980ej2v1ud figure 6-10. timing of 2-cycle dma transfer (sram sdram) (1/3) (a) single transfer mode sdclk (output) dmarqx (input) dmaakx (output) tc0 (output) address (output) internal dma output signal sdras (output) sdcas (output) rd (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d15 (i/o) address col. col. data h ti ti ti ti to t1r t1w t2w t2w t2r ti ti t1 t2 t1 ti ti t1 ti t2 to t2 t1 t2 tw t1w tw t2 tact twr t2w twr twe tw ti tw twpre data data data address t2w t2w twe twpre t2w t2w ti t1 t1r t1 t2r t2 data data data data csn (output) of other area csn (output) of sram area csn (output) of sdram area row note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7, x = 0, 1 4. col.: column address row: row address
chapter 6 dma functions (dma controller) 183 user's manual u14980ej2v1ud figure 6-10. timing of 2-cycle dma transfer (sram sdram) (2/3) (b) single-step transfer mode sdclk (output) dmarqx (input) dmaakx (output) tc0 (output) address (output) internal dma request signal sdras (output) sdcas (output) rd (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d15 (i/o) address col. col. data h ti ti ti ti to t1r t1w t2w t2w t2r ti ti t1 t2 t1 ti t1 ti t2 ti t2 t1 t2 tw t1w tw t2 tact twr t2w twr twe twpre data data data address t2w t2w twe twpre t2w t2w ti t1 t1r t1 t2r t2 data data data data csn (output) of other area csn (output) of sram area csn (output) of sdram area row note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7, x = 0, 1 4. col.: column address row: row address
chapter 6 dma functions (dma controller) 184 user's manual u14980ej2v1ud figure 6-10. timing of 2-cycle dma transfer (sram sdram) (3/3) (c) block transfer mode sdclk (output) dmarqx (input) dmaakx (output) tc0 (output) address (output) internal dma request signal sdras (output) sdcas (output) rd (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d15 (i/o) address col. col. data h ti ti ti ti to t1r t1w t2w t2w t2r ti ti ti t1 t2 t1 t1 t2 tw t1w tw t2 tact twr t2w twr twe twpre data data data address t2w t2w twe twpre t2w t2w t1r t1 t2r t2 data data csn (output) of sdram area csn (output) of other area csn (output) of sram area row note note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7, x = 0, 1 4. col.: column address row: row address
chapter 6 dma functions (dma controller) 185 user's manual u14980ej2v1ud figure 6-11. timing of 2-cycle dma transfer (sdram sram) (1/3) (a) single transfer mode sdclk (output) dmarqx (input) dmaakx (output) tc0 (output) address (output) internal dma request signal sdras (output) sdcas (output) rd (output) we (output) ldqm/lwr (output) udqm/uwr (output) sdcke (output) d0 to d15 (i/o) address col. col. h ti ti ti ti to t1r t2r ti ti t1 t2 t1 ti ti t1 t1 ti t2 t2 to t2 t2 tw t1w tw tact tw ti tw data data address t1w tread t2r tlate t2r tlate t2r tread t2w tlate t2w tlate t2w t2w t1r t2r ti t1 t2 t1 data data data data data data csn (output) of other area csn (output) of sram area csn (output) of sdram area row note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7, x = 0, 1 4. col.: column address row: row address
chapter 6 dma functions (dma controller) 186 user's manual u14980ej2v1ud figure 6-11. timing of 2-cycle dma transfer (sdram sram) (2/3) (b) single-step transfer mode sdclk (output) dmarqx (input) dmaakx (output) tc0 (output) address (output) internal dma request signal sdras (output) sdcas (output) rd (outpur) we (output) sdcke (output) d0 to d15 (i/o) address col. col. h ti ti ti ti to t1r t2r ti ti t1 t2 t1 ti t1 t1 ti t2 t2 ti t2 t2 tw t1w tw tact data data address t1w tread t2r tlate t2r tlate t2r tread t2w tlate t2w tlate t2w t2w t1r t2r ti t1 t2 t1 data data data data data data csn (output) of other area csn (output) of sram area csn (output) of sdram area ldqm/lwr (output) udqm/uwr (output) row note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7, x = 0, 1 4. col.: column address row: row address
chapter 6 dma functions (dma controller) 187 user's manual u14980ej2v1ud figure 6-11. timing of 2-cycle dma transfer (sdram sram) (3/3) (c) block transfer mode sdclk (output) dmarqx (input) dmaakx (output) tc0 (output) address (output) internal dma request signal sdras (output) sdcas (output) rd (output) we (output) sdcke (output) d0 to d15 (i/o) address col. col. h ti ti ti ti to t1r t2r ti ti ti t1 t2 t1 t1 t2 t2 tw t1w tw tact data data address t1w tread t2r tlate t2r tlate t2r tread t2w tlate t2w tlate t2w t2w t1r t2r t2 t1 data data data data csn (output) of other area csn (output) of sram area csn (output) of sdram area ldqm/lwr (output) udqm/uwr (output) row note note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0, 3, 4, 7, x = 0, 1 4. col.: column address row: row address
chapter 6 dma functions (dma controller) 188 user's manual u14980ej2v1ud 6.7 transfer object 6.7.1 transfer type and transfer object table 6-1 lists the relationships between tr ansfer type and transfer object. the mark ? ? means ?transfer possible?, and the mark ? ? ? means ?transfer impossible?. table 6-1. relationship between tran sfer type and transfer object transfer destination (two-cycle transfer) on-chip peripheral i/o external i/o internal ram external memory on-chip peripheral i/o external i/o internal ram ? source external memory cautions 1. the operation is not guaranteed for comb inations of transfer dest ination and source marked with " ? " in table 6-1. 2. addresses between 3fff000h and 3ffffffh cannot be specified for the source and destination address of dma transfer. be sure to specify an addre ss between ffff000h and fffffffh. remarks 1. during 2-cycle dma transfer, if the data bus width of the transfer source and that of the transfer destination are different, the operation becomes as follows. <16-bit transfer> ? transfer from a 16-bit bus to an 8-bit bus a read cycle (16 bits) is generated and then a writ e cycle (8 bits) is generated twice successively. ? transfer from an 8-bit bus to a 16-bit bus a read cycle (8 bits) is generated twice successively and then a write cycle (16 bits) is generated. <8-bit transfer> ? transfer from 16-bit bus to 8-bit bus a read cycle (the higher 8 bits go into a high-impedance state) is generated and then a write cycle (8 bits) is generated. ? transfer from 8-bit bus to 16-bit bus a read cycle (8 bits) is generated and then a write cycle is generated (the higher 8 bits go into a high-impedance state). data is wr itten in the order of lower bits to higher bits to the transfer destination in the case of little endian and in the reverse order in the case of big endian. 2. transfer between the little endian area and the big endian area is also possible. 6.7.2 external bus cycles during dma transfer the external bus cycles during dma transfer are shown below. table 6-2. external bus cycles during dma transfer transfer type transfer object external bus cycle on-chip peripheral i/o, internal ram none note ? external i/o yes sram cycle 2-cycle transfer external memory yes memory acce ss cycle set by the bct register note other external cycles, such as a cpu-based bus cycle can be started.
chapter 6 dma functions (dma controller) 189 user's manual u14980ej2v1ud 6.8 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 these priorities are valid in the ti state only. in the block transfer mode , the channel used for transfer is never switched. in the single-step transfer mode, if a higher priority dma tr ansfer request is issued while the bus is released (in the ti state), the higher priority dma transfer request is acknowledged. caution do not start two or more dma channels with the same factor. if two or more dma channels are started with the same factor, a dma channel with a lower priority may be acknowledged before a dma channel with a higher priority. 6.9 next address setting function the dma source address registers (dsanh, dsanl), dm a destination address registers (ddanh, ddanl), and dma transfer count register (dbcn) are buffer register s with a 2-stage fifo configuration (n = 0 to 3). when the terminal count is issued, thes e registers are automatically rewritten with the value that was set immediately before. therefore, during dma transfer, transfe r is automatically started when a new dma transfer setting is made for these registers and the enn bit of the dchcn register, a nd mlen bit is set to 1 (however, the dma transfer end interrupt may be issued even if dma transfer is automatically started). figure 6-12 shows the configurat ion of the buffer register. figure 6-12. buffer register configuration data read data write master register slave register address/ count controller internal bus
chapter 6 dma functions (dma controller) 190 user's manual u14980ej2v1ud 6.10 dma transfer start factors there are 3 types of dma transfer start factors, as shown below. (1) request from an external pin (dmarqn) requests from the dmarqn pin are sampled each time the clkout signal rises (n = 0, 1). hold the request from dmarqn pin until the corresponding dmaakn si gnal becomes active. if a state whereby the enn bit of the dchcn register = 1 and the tcn bit = 0 (n = 0 to 3) is set, the dmarqn signal (n = 0, 1) in the ti state becomes valid. if t he dmarqn signal becomes active in the ti state, it changes to the t0 state and dma transfer is started. (2) request from software if the stgn, enn, and tcn bits of t he dchcn register are set as follows, dma transfer starts (n = 0 to 3). ? stgn bit = 1 ? enn bit = 1 ? tcn bit = 0 (3) request from on-chip peripheral i/o if, when the enn and tcn bits of the dchcn register are set as shown below, an interrupt request is issued from the on-chip peripheral i/o that is set in the dtfrn register, dma transfer starts (n = 0 to 3). ? enn bit = 1 ? tcn bit = 0 remark when the dmarqn signal is used for the dma start trigger, dma transfer request is level-detected since the dmarqn signal is detected at the level (n = 0, 1). edge-detection for dma transfer request is possible, however, by not using the dmarqn sig nal but using an external interrupt request for the dma start trigger.
chapter 6 dma functions (dma controller) 191 user's manual u14980ej2v1ud 6.11 terminal count output upon dma transfer end the terminal count signal (tc0) becomes active for one clock during the last dma transfer cycle. in two-cycle transfer, the tc0 signal becomes active for one clock at the start of the write cycle of the last dma transfer. figure 6-13. terminal count signal (tc0) timing example cpu cpu dmax dmax dmax cpu cpu dmarqn (input) tc0 (output) dma channel x terminal count remark n = 0, 1, x = 0 to 3 figure 6-14. example of termina l count signal (tc0) output clkout (output) tc0 (output) two-cycle transfer (last) read cycle write cycle
chapter 6 dma functions (dma controller) 192 user's manual u14980ej2v1ud 6.12 forcible interrupt dma transfer can be forcibly interrupted by nmi input during dma transfer. at such a time, the dmac resets the enn bit of the dc hcn register of all channels to 0 and the dma transfer disabled state is entered. an nmi request can then be acknowledged after the dma transfer executed during nmi input is terminated (n = 0 to 3). in the single-step transfer mode or block transfer mode, th e dma transfer request is held in the dmac. if the enn bit is set to 1, dma transfer restarts from the point where it was interrupted. in the single transfer mode, if the enn bit is set to 1, the next dma transfer request is received and dma transfer starts. figure 6-15. example of forcibl e interrupt of dma transfer dma transfer stop dma transfer dma transfer dma transfer stop 01h drst register e00 bit of dchc register ddis register nmi (input) 01h forcible interrupt forcible interrupt transfer restart
chapter 6 dma functions (dma controller) 193 user's manual u14980ej2v1ud 6.13 forcible termination dma transfer can be forcibly terminated by the initn bit of the dchcn register, in addition to the forcible interrupt operation by means of nmi input (n = 0 to 3). an example of forcible termination by the initn bit of the dchcn register is illustrated below (n = 0 to 3). figure 6-16. example of forcible termination of dma transfer (a) block transfer through dma channel 1 is st arted during block transfer through dma channel 0 cpu cpu cpu cpu dma1 dma1 dma1 dma1 dma1 cpu dma1 dma1 dma1 dma1 cpu cpu cpu dmarq0 (input) dmarq1 (input) dma channel 1 transfer start dma channel 1 terminal count forcible termination of dma channel 0 transfer, bus released dsa0, dda0, dbc0, dadc0, dchc0 register set dchc0 (init0 bit = 1) register set dsa1, dda1, dbc1, dadc1, dchc1 register set e00 bit = 1 tc0 bit = 0 e00 bit 0 tc0 bit = 0 e11 bit = 1 tc1 bit = 0 e11 bit 0 tc1 bit 1 (b) when transfer is aborted dur ing dma channel 1 block transfer, and transfer under another condition is executed cpu cpu cpu cpu dma1 dma1 dma1 dma1 dma1 dma1 cpu cpu cpu cpu dma1 dma1 dma1 cpu dmarq1 (input) forcible termination of dma channel 1 transfer, bus released dma channel 1 terminal count dsa1, dda1, dbc1, dadc1, dchc1 register set dadc1, dchc1 register set dchc1 (init1 bit = 1) register set dsa1, dda1, dbc1 register set e11 bit = 1 tc1 bit = 0 e11 bit 0 tc1 bit = 1 e11 bit 1 tc1 bit = 0 e11 bit 0 tc1 bit 1 remark because the dsan, ddan, and dbcn registers ar e fifo-configured buffer regi sters, the values are held even after a forcible termination. also, t he next transfer condition can be set even during dma transfer. but, because the dadcn and dchcn regist ers are not buffer registers, the setting during dma transfer is invalid (refer to 6.9 next address setting function and 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3 ).
chapter 6 dma functions (dma controller) 194 user's manual u14980ej2v1ud 6.14 times related to dma transfer the overhead before and after dma transfer and minimum ex ecution clock for dma transfer are shown below. in the case of external memory access, the time depends on the type of external memory connected. table 6-3. number of minimu m execution clocks in dma cycle dma cycle number of minimum execution clocks from dmarqn signal acknowledgement to dmaakn signal falling 4 clocks external memory access depends on the memory connected. internal ram access 1 clock remark n = 0, 1 6.15 maximum response time for dma transfer request the response time for a dma transfer request becomes the longest under the following conditions (in the sdram refresh cycle enabled state). however, the case when a hi gher priority dma transfer is generated is excluded. (1) condition 1 condition instruction fetch from an exte rnal memory in 8-bit data bus width response time tinst 4 + tref dmaakn (output) d0 to d15 (i/o) dmarqn (input) dma cycle refresh fetch (1/4) fetch (2/4) fetch (3/4) fetch (4/4) remark n = 0, 1 (2) condition 2 condition word data access with an exte rnal memory in 8-bit data bus width response time tdata 4 + tref dmaakn (output) d0 to d15 (i/o) dmarqn (input) dma cycle refresh data (1/4) data (2/4) data (3/4) data (4/4) remark n = 0, 1
chapter 6 dma functions (dma controller) 195 user's manual u14980ej2v1ud (3) condition 3 condition instruction fetch from an exte rnal memory in 8-bit data bus width execution of a bit manipulation in struction (set1, clr1, or not1) response time tinst 4 + tdata 2 + tref dmaakn (output) d0 to d15 (i/o) dmarqn (input) dma cycle refresh data write data read fetch (4/4) fetch (3/4) fetch (2/4) fetch (1/4) remarks 1. tinst: number of clocks per bus cycle during inst ruction fetch tdata: number of clocks per bus cycle dur ing data access tref: number of clocks per refresh cycle 2. n = 0, 1 6.16 one-time transfer during single transfer via dmarq0, dmarq1 signals the dmarqn signal is sampled at the rising edge of the third clock a fter the dma transfer cycle in the single- transfer mode has been completed. to perform transfer only one-time when single transfer is executed for an external memory via the dmarqn signal, the dmarqn sig nal must be made inactive within 2 clocks from when the dmaakn signal becomes inactive (n = 0, 1). figure 6-17. time to perfo rm single transfer one time dmaakn (output) clkout (output) dmarqn (input) dma request sampling period period without sampling dma request dma transfer cycle in the single transfer mode, the next dma transfer does not start if the dmarqn signal rises within two clocks. remarks 1. the circle { indicates the sampling timing. 2. n = 0, 1
chapter 6 dma functions (dma controller) 196 user's manual u14980ej2v1ud 6.17 cautions (1) memory boundary the transfer operation is not guarant eed if the source or the destination address exceeds the area of dma objects (external memory, internal ram, or peripheral i/o) during dma transfer. (2) transfer of misaligned data dma transfer of 16-bit bus width misaligned data is not su pported. if the source or the destination address is set to an odd address, the lsb of the address is forcibly handled as "0". (3) bus arbitration for cpu when an external device is targeted for dma transfer, the cpu can access the internal ram (if they are not subject to dma transfer). (4) maintenance of dmarqn signal be sure to maintain the dmarqn signal at the active level until the dmaakn signal becomes active (n = 0, 1). if the dmarqn signal becomes inactive before the dmaakn signal becomes active, dma transfer may not be performed. (5) dmaakn signal output when the transfer object is internal ram, the dmaakn signal is not output during a dma cycle for internal ram (for example, if 2-cycle transfer is performed fr om internal ram to an external memory, the dmaakn signal is output only during a dma write cycle for the external memory) (n = 0, 1). (6) dma start factors do not start two or more dma channels with the same factor. if two or more dma channels are started with the same factor, a dma channel with a lower priority may be acknowledged before a dma channel with a higher priority. 6.17.1 interrupt factors dma transfer is interrupted if the following factors are issued. ? bus hold ? refresh cycle if the factor that is interrupting dma transfer disappears, dma transfer promptly restarts. 6.18 dma transfer end when dma transfer ends and the tcn bit of the dchcn register is set to 1, a dma transfer end interrupt (intdman) is issued to the interrupt controller (intc) (n = 0 to 3).
197 user's manual u14980ej2v1ud chapter 7 interrupt/exception processing function the v850e/ma2 is provided with a dedica ted interrupt controller (intc) for interrupt servicing and can process a total of 27 interrupt requests. an interrupt is an event that occu rs independently of program execution, and an except ion is an event whose occurrence is dependent on pr ogram execution. the v850e/ma2 can process interrupt requests from t he on-chip peripheral hardwar e and external sources. moreover, exception processing can be st arted by the trap instruction (softwar e exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 7.1 features { interrupts ? non-maskable interrupts: 1 source maskable interrupts: 26 sources 8 levels of programmable priorities (maskable interrupts) multiple interrupt control according to priority masks can be specified for each maskable interrupt request. noise elimination, edge detection, and valid edge specification for ex ternal interrupt request signals. { exceptions software exceptions: 32 sources exception traps: 2 sources ( illegal opcode exception and debug trap) interrupt/exception sources ar e listed in table 7-1.
chapter 7 interruption/exception processing function 198 user's manual u14980ej2v1ud table 7-1. interrupt/exception source list interrupt/exception source type classification name controlling register generating source generating unit default priority exception code handler address restored pc reset interrupt reset ? reset input ? ? 0000h 00000000h undefined non-maskable interrupt nmi0 ? nmi input ? ? 0010h 00000010h nextpc exception trap0n note ? trap instruction ? ? 004nh note 00000040h nextpc software exception exception trap1n note ? trap instruction ? ? 005nh note 00000050h nextpc exception trap exception ilgop/ dbg0 ? illegal opcode/ dbtrap instruction ? ? 0060h 00000060h nextpc interrupt intov00 ovic00 timer 00 ov erflow rpu 0 0080h 00000080h nextpc interrupt intov01 ovic01 timer 01 ov erflow rpu 1 0090h 00000090h nextpc interrupt intp000/ intm000 p00ic0 match of intp000 pin/ccc00 pin/rpu 4 00c0h 000000c0h nextpc interrupt intp001/ intm001 p00ic1 match of intp001 pin/ccc01 pin/rpu 5 00d0h 000000d0h nextpc interrupt intp010/ intm010 p01ic0 match of intp010 pin/ccc10 pin/rpu 6 00e0h 000000e0h nextpc interrupt intp011/ intm011 p01ic1 match of intp011 pin/ccc11 pin/rpu 7 00f0h 000000f0h nextpc interrupt intp100 p10ic0 intp100 pin pin 12 0140h 00000140h nextpc interrupt intp101 p10ic1 intp101 pin pin 13 0150h 00000150h nextpc interrupt intp110 p11ic0 intp110 pin pin 16 0180h 00000180h nextpc interrupt intcmd0 cmicd0 cmd0 ma tch signal rpu 28 0240h 00000240h nextpc interrupt intcmd1 cmicd1 cmd1 ma tch signal rpu 29 0250h 00000250h nextpc interrupt intcmd2 cmicd2 cmd2 ma tch signal rpu 30 0260h 00000260h nextpc interrupt intcmd3 cmicd3 cmd3 ma tch signal rpu 31 0270h 00000270h nextpc interrupt intdma0 dmaic0 dma0 transfe r completion dma 32 0280h 00000280h nextpc interrupt intdma1 dmaic1 dma1 transfe r completion dma 33 0290h 00000290h nextpc interrupt intdma2 dmaic2 dma2 transfer completion dma 34 02a0h 000002a0h nextpc interrupt intdma3 dmaic3 dma3 transfer completion dma 35 02b0h 000002b0h nextpc interrupt intcsi0 csiic0 csi0 transmission/ reception completion sio 36 02c0h 000002c0h nextpc interrupt intser0 seic0 uart0 recept ion error sio 37 02d0h 000002d0h nextpc interrupt intsr0 sric0 uart0 reception completion sio 38 02e0h 000002e0h nextpc interrupt intst0 stic0 uart0 transmission completion sio 39 02f0h 000002f0h nextpc interrupt intcsi1 csiic1 csi1 transmission/ reception completion sio 40 0300h 00000300h nextpc interrupt intser1 seic1 uart1 recept ion error sio 41 0310h 00000310h nextpc interrupt intsr1 sric1 uart1 reception completion sio 42 0320h 00000320h nextpc interrupt intst1 stic1 uart1 transmission completion sio 43 0330h 00000330h nextpc maskable interrupt intad adic a/d convert completion adc 48 0380h 00000380h nextpc note n = 0 to fh remarks 1. default priority: the priority order when two or more maskable interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, t he value of the pc saved when an interrupt is acknowledged during division (div, divh, divu, divhu) in struction execution is the value of the pc of the current instruction (div, divh, divu, divhu). nextpc: the pc value that starts the processing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated with (restored pc ? 4).
chapter 7 interruption/exception processing function 199 user's manual u14980ej2v1ud 7.2 non-maskable interrupt a non-maskable interrupt request is acknowledged unconditi onally, even when interrupts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence over all the other interrupts. a non-maskable interrupt request is input from the nmi pin. when the valid edge specifi ed by bit 0 (esn0) of the external interrupt mode register 0 (intm0) is detected on the nmi pin, the interrupt occurs. while the service program of the non -maskable interrupt is being executed ( psw.np = 1), the acknowledgement of another non-maskable interrupt request is held pending. the pending nmi is ack nowledged after the original service program of the non-maskable interrupt under execution has been terminated (by the reti instruction), or when psw.np is cleared to 0 by the ldsr instruction. note that if two or more nmi requests are input during the execution of the service program for an nmi, the number of nmis that will be acknowledged after psw.np is cleared to 0 is only one. remark psw.np: the np bit of the psw register.
chapter 7 interruption/exception processing function 200 user's manual u14980ej2v1ud 7.2.1 operation if a non-maskable interrupt is generated, the cpu performs the following proce ssing, and transfers control to the handler routine: <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes exception code 0010h to the higher halfword (fecc) of ecr. <4> sets the np and id bits of the psw and clears the ep bit. <5> sets the handler address (00000010h) corresponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non-mask able interrupt is shown in figure 7-1. figure 7-1. servicing configurat ion of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h 1 0 1 00000010h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing
chapter 7 interruption/exception processing function 201 user's manual u14980ej2v1ud figure 7-2. acknowledging non -maskable interrupt request (a) if a new nmi request is generated while an nmi ser vice program is being executed main routine nmi request nmi request (psw.np = 1) nmi request held pending regardless of the value of the np bit of the psw pending nmi request processed (b) if a new nmi request is generated twice while an nmi service program is being executed main routine nmi request nmi request held pending because nmi service program is being processed only one nmi request is acknowledged even though two nmi requests are generated nmi request held pending because nmi service program is being processed
chapter 7 interruption/exception processing function 202 user's manual u14980ej2v1ud 7.2.2 restore execution is restored from the non-maskable inte rrupt servicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. <1> restores the values of the pc and the psw from fepc and fepsw, res pectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. <2> transfers control back to the address of the restored pc and psw. figure 7-3 illustrates how the reti instruction is processed. figure 7-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the psw.ep bit and psw.np bit ar e changed by the ldsr instruction during non- maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 7 interruption/exception processing function 203 user's manual u14980ej2v1ud 7.2.3 non-maskable interrupt status flag (np) the np flag is a status flag that i ndicates that non-maskable interrupt (nmi ) servicing is under execution. this flag is set when an nmi interrupt has been acknowl edged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 7 np nmi pending indicates whether nmi interrupt servicing is in progress. 0: no nmi interrupt servicing 1: nmi interrupt currently being processed 7.2.4 noise elimination nmi pin noise is eliminated with analog delay. the delay ti me is 60 to 300 ns. a signal input that changes within the delay time is not internally acknowledged. 7.2.5 edge detection function (1) external interrupt m ode register 0 (intm0) external interrupt mode register 0 (intm0) is a register that spec ifies the valid edge of a non-maskable interrupt (nmi). the nmi valid edge can be specified to be either t he rising edge or the falling edge by the esn0 bit. this register can be read/written in 8-bit or 1-bit units. address fffff880h 7 0 intm0 6 0 5 0 4 0 3 0 2 0 1 0 <0> esn0 after reset 00h bit position bit name function 0 esn0 edge select nmi specifies the nmi pin?s valid edge. 0: falling edge 1: rising edge
chapter 7 interruption/exception processing function 204 user's manual u14980ej2v1ud 7.3 maskable interrupts maskable interrupt requests can be ma sked by interrupt control register s. the v850e/ma2 has 26 maskable interrupt sources. if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight le vels of priorities can be spec ified by using the interrupt control registers (programmable priority control). when an interrupt request has been ackno wledged, the acknowledgement of other maskable interrupt requests is disabled and the interrupt disabled (di) status is set. when the ei instruction is ex ecuted in an interrupt servici ng routine, the interrupt enabled (ei) status is set, which enables servicing of interrupts having a hi gher priority than the interrupt request in progress (specified by the interrupt control register). note that only in terrupts with a higher priority will have th is capability; interrupts with the same priority level cannot be nested. however, if multiple interrupts are exec uted, the following processing is necessary. <1> save eipc and eipsw in memory or a general-purpos e register before executi ng the ei instruction. <2> execute the di instruct ion before executing the reti instruction, then reset ei pc and eipsw with the values saved in <1>. 7.3.1 operation if a maskable interrupt occurs by int input, the cpu perfo rms the following processing, and transfers control to a handler routine: <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the id bit of the psw and clears the ep bit. <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the servicing configurati on of a maskable interrupt is shown in figure 7-4.
chapter 7 interruption/exception processing function 205 user's manual u14980ej2v1ud figure 7-4. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? is an interrupt request issued? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc acknowledged yes yes yes priority higher than that of interrupt currently being processed? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address note for the ispr register, refer to 7.3.6 in-service prio rity register (ispr) . the int input masked by the interrupt controllers and the int input that o ccurs while another interrupt is being processed (when psw.np = 1 or psw.id = 1) are held pending inter nally by the interrupt controller. in such case, if the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 as set by the reti and ldsr instructions, input of the pending int starts the new maskable interrupt servicing.
chapter 7 interruption/exception processing function 206 user's manual u14980ej2v1ud 7.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is execut ed, the cpu performs the following steps , and transfers control to the address of the restored pc. <1> restores the values of the pc and the psw from eipc and eipsw bec ause the ep bit of the psw is 0 and the np bit of the psw is 0. <2> transfers control to the address of the restored pc and psw. figure 7-5 illustrates the processi ng of the reti instruction. figure 7-5. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for the ispr register, refer to 7.3.6 in-service prio rity register (ispr) . caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 7 interruption/exception processing function 207 user's manual u14980ej2v1ud 7.3.3 priorities of maskable interrupts the v850e/ma2 provides multiple inte rrupt servicing in which an interrupt is acknowledged while another interrupt is being processed. multiple interrupt s can be controlled by priority levels. there are two types of priority leve l control: control based on the default priority leve ls, and control based on the programmable priority levels that are spec ified by the interrupt priority level s pecification bit (xxprn ) of the interrupt control register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupts are processed in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, refer to table 7-1 interrupt/exception source list . the programmable priority control custom izes interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is a cknowledged, the id flag of psw is automat ically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing t he ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 )
chapter 7 interruption/exception processing function 208 user's manual u14980ej2v1ud figure 7-6. example of processing in which anot her interrupt request is issued while an interrupt is being processed (1/2) main routine ei ei interrupt request a (level 3) processing of a processing of b processing of c interrupt request c (level 3) processing of d processing of e ei interrupt request e (level 2) processing of f ei processing of g interrupt request g (level 1) interrupt request h (level 1) processing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution the values of the eipc and eipsw regi sters must be saved be fore executing multiple interrupts. when returning from multiple inte rrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests.
chapter 7 interruption/exception processing function 209 user's manual u14980ej2v1ud figure 7-6. example of processing in which anot her interrupt request is issued while an interrupt is being processed (2/2) main routine ei interrupt request i (level 2) processing of i processing of k interrupt request j (level 3) processing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) processing of l processing of n processing of m processing of s processing of u processing of t interrupt request m (level 3) interrupt request n (level 1) processing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 processing of p processing of q processing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because processing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after processing of interrupt request l. at this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after processing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution the values of the eipc and eipsw regi sters must be saved be fore executing multiple interrupts. when returning from multiple inte rrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority
chapter 7 interruption/exception processing function 210 user's manual u14980ej2v1ud figure 7-7. example of processing interr upt requests simultan eously generated default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) processing of interrupt request b . . processing of interrupt request c processing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. caution the values of the eipc and eipsw regi sters must be saved be fore executing multiple interrupts. when returning from multiple inte rrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remark a to c in the figure are the temporary names of in terrupt requests shown for the sake of explanation.
chapter 7 interruption/exception processing function 211 user's manual u14980ej2v1ud 7.3.4 interrupt control register (xxicn) an interrupt control register is assigned to each in terrupt request (maskable inte rrupt) and sets the control conditions for each maskable interrupt request. this register can be read/written in 8-bit or 1-bit units. caution read the xxifn bit of the xxicn register in the interrupt disabled state. otherwise if the interrupt acknowledgment and bit reading timing conf licts, normal values may not be read. address fffff110h to ffff170h <7> xxifn xxicn <6> xxmkn 5 0 4 0 3 0 2 xxprn2 1 xxprn1 0 xxprn0 after reset 47h bit position bit name function 7 xxifn interrupt request flag this is an interrupt request flag. 0: interrupt request not issued 1: interrupt request issued the flag xxlfn is reset automatically by the hardware if an interrupt request is acknowledged. 6 xxmkn mask flag this is an interrupt mask flag. 0: enables interrupt servicing 1: disables interr upt servicing (pending) priority 8 levels of priority order ar e specified for each interrupt. xxprn2 xxprn1 xxprn0 interrupt priority specification bit 0 0 0 specifies level 0 (highest). 0 0 1 specifies level 1. 0 1 0 specifies level 2. 0 1 1 specifies level 3. 1 0 0 specifies level 4. 1 0 1 specifies level 5. 1 1 0 specifies level 6. 1 1 1 specifies level 7 (lowest). 2 to 0 xxprn2 to xxprn0 remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 ). the address and bit of each interrupt control register are as follows:
chapter 7 interruption/exception processing function 212 user's manual u14980ej2v1ud table 7-2. address and bits of interrupt control register bit address register <7> <6> 5 4 3 2 1 0 fffff110h ovic00 ovif0 ovmk0 0 0 0 ovpr02 ovpr01 ovpr00 fffff112h ovic01 ovif1 ovmk1 0 0 0 ovpr12 ovpr11 ovpr10 fffff118h p00ic0 p00if0 p00mk0 0 0 0 p00pr02 p00pr01 p00pr00 fffff11ah p00ic1 p00if1 p00mk1 0 0 0 p00pr12 p00pr11 p00pr10 fffff11ch p01ic0 p01if0 p01mk0 0 0 0 p01pr02 p01pr01 p01pr00 fffff11eh p01ic1 p01if1 p01mk1 0 0 0 p01pr12 p01pr11 p01pr10 fffff128h p10ic0 p10if0 p10mk0 0 0 0 p10pr02 p10pr01 p10pr00 fffff12ah p10ic1 p10if1 p10mk1 0 0 0 p10pr12 p10pr11 p10pr10 fffff130h p11ic0 p11if0 p11mk0 0 0 0 p11pr02 p11pr01 p11pr00 fffff148h cmicd0 cmif0 cmmk0 0 0 0 cmpr02 cmpr01 cmpr00 fffff14ah cmicd1 cmif1 cmmk1 0 0 0 cmpr12 cmpr11 cmpr10 fffff14ch cmicd2 cmif2 cmmk2 0 0 0 cmpr22 cmpr21 cmpr20 fffff14eh cmicd3 cmif3 cmmk3 0 0 0 cmpr32 cmpr31 cmpr30 fffff150h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff152h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff154h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff156h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff158h csiic0 csiif0 csimk0 0 0 0 csipr02 csipr01 csipr00 fffff15ah seic0 seif0 semk0 0 0 0 sepr02 sepr01 sepr00 fffff15ch sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff15eh stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff160h csiic1 csiif1 csimk1 0 0 0 csipr12 csipr11 csipr10 fffff162h seic1 seif1 semk1 0 0 0 sepr12 sepr11 sepr10 fffff164h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff166h stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff170h adic adif admk 0 0 0 adpr2 adpr1 adpr0
chapter 7 interruption/exception processing function 213 user's manual u14980ej2v1ud 7.3.5 interrupt mask register s 0 to 3 (imr0 to imr3) these registers set the interrupt mask state for the maskable interrupts. t he xxmkn bit of the imr0 to imr3 registers is equivalent to the xxm kn bit of the xxicn register. the imrm register (m = 0 to 3) can be read/written in 16-bit units. if the higher 8 bits of the imrm regist er are used as an imrmh register and t he lower 8 bits as an imrml register, these registers can be read/wri tten in 8- or 1-bit units. bits 15, 14, 11 to 8, 3, and 2 of the im r0 register (bits 7, 6, and 3 to 0 of the imr0h register and bits 3 and 2 of the imr0l register), bits 11 to 1 of the im r1 register (bits 3 to 0 of the imr1h register and bits 7 to 1 of the imr1l register), bits 15 to 12 of the imr2 regi ster (bits 7 to 4 of the imr2h register), and bits 15 to 1 of the imr3 register (bits 7 to 0 of the imr3h register and bits 7 to 1 of the imr3l register) are fix ed to 1. if these bits are not 1, the operation cannot be guaranteed. caution the device file defines the xxmkn bit of th e xxicn register as a reser ved word. if a bit is manipulated using the name of xxmkn, the contents of the xxicn register , instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten).
chapter 7 interruption/exception processing function 214 user's manual u14980ej2v1ud address fffff100h 15 1 imr0 14 1 13 p10mk1 12 p10mk0 11 1 10 1 9 1 8 1 7 p01mk1 6 p01mk0 5 p00mk1 4 p00mk0 3 1 2 1 1 ovmk1 0 ovmk0 after reset ffffh address fffff102h 15 cmmk3 imr1 14 cmmk2 13 cmmk1 12 cmmk0 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 p11mk0 after reset ffffh address fffff104h 15 1 imr2 14 1 13 1 12 1 11 stmk1 10 srmk1 9 semk1 8 csimk1 1 stmk0 6 srmk0 5 semk0 4 csimk0 3 dmamk3 2 dmamk2 1 dmamk1 0 dmamk0 after reset ffffh address fffff106h 15 1 imr3 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 admk after reset ffffh bit position bit name function 13, 12, 7 to 4, 1, 0 (imr0) 15 to 12, 0 (imr1) 11 to 0 (imr2) 0 (imr3) xxmkn mask flag interrupt mask flag 0: interrupt servicing permitted 1: interrupt servicing prohibited (pending) remark xx: identification name of each peripheral unit (refer to table 7-2 ). n: peripheral unit number (refer to table 7-2 )
chapter 7 interruption/exception processing function 215 user's manual u14980ej2v1ud 7.3.6 in-service priori ty register (ispr) this register holds the priority leve l of the maskable interrupt currently a cknowledged. when an interrupt request is acknowledged, the bit of this register co rresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the inte rrupt request having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only in 8-bit or 1-bit units. caution read the ispr register in the interrupt disabled state. otherwise if the interrupt acknowledgment and register reading timing conflicts, normal values may not be read. address fffff1fah <7> ispr7 ispr <6> ispr6 <5> ispr5 <4> ispr4 <3> ispr3 <2> ispr2 <1> ispr1 <0> ispr0 after reset 00h bit position bit name function 7 to 0 ispr7 to ispr0 in-service priority flag indicates priority of interrupt currently acknowledged 0: interrupt request with priority n not acknowledged 1: interrupt request with priority n acknowledged remark n = 0 to 7 (priority level) 7.3.7 maskable interrupt status flag (id) the id flag is bit 5 of the psw and th is controls the maskable interrupt?s operating state, and stores control information regarding enabling or disabling of interrupt requests. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 5 id interrupt disable indicates whether maskable interrupt servicing is enabled or disabled. 0: maskable interrupt request acknowledgement enabled 1: maskable interrupt request acknowledgement disabled (pending) this bit is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. non-maskable interrupt requests and e xceptions are acknowledged regardless of this flag. when a maskable interr upt is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request generated during t he acknowledgement disabled period (id = 1) is acknowledged when the xxifn bit of xxicn is set to 1, and the id flag is reset to 0.
chapter 7 interruption/exception processing function 216 user's manual u14980ej2v1ud 7.3.8 noise elimination the noise of the intpn, intpm, ti 000, and ti010 pins is elim inated with analog delay (n = 000, 001, 010, 011, m = 100, 101, 110). the delay time is about 60 to 220 ns. a signal input that changes wit hin the delay time is not internally acknowledged. 7.3.9 interrupt trigger mode selection the valid edge of pins intp0n0, intp0n1, intp1n0, intp 101, and ti0n0 can be selected by program. moreover, a level trigger can be selected for the intp1n0 and intp101 pi ns (n = 0, 1). the edge t hat can be selected as the valid edge is one of the following. ? rising edge ? falling edge ? both the rising and falling edges when the intp0n0, intp0n1, intp1n0, intp101, and ti0n0 pins are edge-detec ted, they become an interrupt source, a capture trigger input, and a timer exte rnal count input respectively (n = 0, 1). the valid edge is specified by exter nal interrupt mode registers 1 and 2 (intm1, intm2) and valid edge select registers c0 and c1 (sesc0, sesc1). the level trigger is specified by external interr upt registers 1 and 2 (intm1, intm2). (1) external interrupt mode registers 1, 2 (intm1, intm2) these are registers that specify the trigger mode for external interrupt requests (intp100, intp101, intp110), input via external pins. the correspondenc e between each register and the external interrupt requests that register controls is shown below. ? intm1: intp100, intp101 ? intm2: intp110 the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). these registers can be read/ written in 8-bit units. be sure to set bits 7 to 4 of the intm1 register and bits 7 to 2 of the intm2 register to 0. if they are set to 1, the operation is not guaranteed. caution before setting the intp100, intp101, or intp110 pin in the trigger mode, set the pmcm register. if the pmcm register is set after the intm 1 and intm2 registers have been set, an illegal interrupt may occur, depending on the timing of setting the pmcm register (m = 0, 2).
chapter 7 interruption/exception processing function 217 user's manual u14980ej2v1ud address fffff882h 7 0 intm1 6 0 5 0 4 0 3 es1011 2 es1010 1 es1001 0 76543210 es1000 after reset 00h address fffff884h intm2 after reset 00h 0 0 0 0 0 0 es1101 es1100 intp101 intp100 intp110 bit position bit name function edge select specifies the valid edge of the intp1nm pins. es1nm1 es1nm0 operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 3 to 0 (intm1) 1, 0 (intm2) es1nm1, es1nm0 (nm = 00, 01, 10) notes 1. the level of the intp1nm pin is sampled at the interval of the system clock divided by two, and the p1nifm bit is latched as an interrupt request when a low level is detected. therefore, even if the p1nifm bit of the interrupt cont rol register (p1nicm) is automat ically cleared to 0 when the cpu acknowledges an interrupt, the p1nifm bit is i mmediately set to 1, and an interrupt is generated continuously. to avoid this, forcibly clear the p1ni fm bit to 0 after making the intp1nm pin inactive for an external device in the interrupt servicing routine (nm = 00, 01, 10). 2. when a lower-priority level-detection interrupt r equest (intp1nm) occurs while another interrupt is being-serviced and this newly-generat ed level-detection interrupt r equest becomes inactive before the current interrupt servicing is complete, this new interrupt request (intp1nm) is held pending. to avoid acknowledging this intp1nm interrupt request, clear the p1nifm bit of the interrupt control register (nm = 00, 01, 10).
chapter 7 interruption/exception processing function 218 user's manual u14980ej2v1ud (2) valid edge selection regi sters c0, c1 (sesc0, sesc1) these are registers that specify the valid edge for external interr upt requests (intp000, intp001, intp010, intp011, ti000, ti010), input via external pins. t he correspondence between each r egister and the external interrupt requests which that regi ster controls is shown below. ? sesc0: ti000, intp000, intp001 ? sesc1: ti010, intp010, intp011 the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). these registers can be read/ written in 8-bit units. cautions 1. when using the intp0n0/ti0n0 or intp 0n1 pin as intp0n0, intp0n 1, be sure to preset the tmccaen bit of timer mode control regi ster cn0 (tmccn0) to 1 (n = 0, 1). 2. before setting the ti0n0, intp0n1, or in tp0n0 pin in the trigger mode, set the pmcn register. if the pmcn register is set after the sescn register has been set, an illegal interrupt may occur, depending on the timing of setting the pmcn register (n = 0, 1). address fffff609h 7 tes01 sesc0 6 tes00 5 0 4 0 3 ies0011 2 ies0010 1 es0001 0 76543210 ies0000 after reset 00h address fffff619h sesc1 after reset 00h tes11 tes10 0 0 ies0111 ies0110 ies0101 ies0100 ti000 intp001 intp000 ti010 intp011 intp010 bit position bit name function 7, 6 tesn1, tesn0 (n = 0, 1) edge select specifies the valid edge of the intpn and ti000 and ti010 pins. xesn1 xesn0 operation 0 0 falling edge 3, 2 iesn1, iesn0 (n = 001, 011) 0 1 rising edge 1 0 rfu (reserved) 1 1 both rising and falling edges 1, 0 iesn1, iesn0 (n = 000, 010)
chapter 7 interruption/exception processing function 219 user's manual u14980ej2v1ud 7.4 software exception a software exception is generated when the cpu ex ecutes the trap instru ction, and can be always acknowledged. 7.4.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfe rs control to the handler routine: <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the ep and id bits of the psw. <5> sets the handler address (00000040h or 00000050h) corre sponding to the software exception to the pc, and transfers control. figure 7-8 illustrates the processi ng of a software exception. figure 7-8. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (t he vector is a value from 0 to 1fh.) the handler address is determined by the trap instruction?s operand (vector). if the vector is 0 to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h.
chapter 7 interruption/exception processing function 220 user's manual u14980ej2v1ud 7.4.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instru ction, the cpu carries out the following pr ocessing and shifts control to the restored pc?s address. <1> loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. <2> transfers control to the address of the restored pc and psw. figure 7-9 illustrates the processi ng of the reti instruction. figure 7-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is n ecessary to set psw.ep back to 1 using the ldsr instruction immediately befo re the reti instruction. remark the solid line shows the cpu processing flow.
chapter 7 interruption/exception processing function 221 user's manual u14980ej2v1ud 7.4.3 exception status flag (ep) the ep flag is bit 6 of psw, and is a status flag used to indica te that exception processing is in progress. it is set when an exception occurs. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 6 ep exception pending shows that exception processing is in progress. 0: exception processing not in progress. 1: exception processing in progress.
chapter 7 interruption/exception processing function 222 user's manual u14980ej2v1ud 7.5 exception trap an exception trap is an interrupt that is requested when an illegal ex ecution of an instruction takes place. in the v850e/ma2, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 7.5.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an in struction applicable to this illegal instruction is executed. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution since it is possible to assign this instru ction to an illegal opcode in the future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the follo wing processing, and transfers control to the handler routine: <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep, and id bits of the psw. <4> sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. figure 7-10 illustrates the proce ssing of the exception trap.
chapter 7 interruption/exception processing function 223 user's manual u14980ej2v1ud figure 7-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore recovery from an exception trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. figure 7-11 illustrates the restore pr ocessing from an exception trap. figure 7-11. restore processing from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 7 interruption/exception processing function 224 user's manual u14980ej2v1ud 7.5.2 debug trap the debug trap is an exception that can be acknowledged every time and is generated by exec ution of the dbtrap instruction. when the debug trap is generat ed, the cpu performs the following processing. (1) operation when the debug trap is generated, the cpu performs the following proce ssing, transfers control to the debug monitor routine, and shifts to debug mode. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep and id bits of the psw. <4> sets the handler address (00000060h) corresponding to the debug trap to the pc and transfers control. figure 7-12 illustrates the pr ocessing of the debug trap. figure 7-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing
chapter 7 interruption/exception processing function 225 user's manual u14980ej2v1ud (2) restore recovery from a debug trap is carried out by the dbret in struction. by executi ng the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. figure 7-13 illustrates the restor e processing from a debug trap. figure 7-13. restore processing from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 7 interruption/exception processing function 226 user's manual u14980ej2v1ud 7.6 multiple interrupt servicing control multiple interrupt servicing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher prio rity level, and the higher priority interrupt request is received and processed first. if there is an interrupt request with a lower priority level than the interrupt request curr ently being processed, that interrupt request is held pending. maskable interrupt multiple servicing control is executed when interrupts are enabled (id = 0). thus, if multiple interrupts are executed, it is necessary to enable interr upts (id = 0) even for an inte rrupt servicing routine. if maskable interrupt enable or a software exception is generated in a maskable interr upt or software exception servicing program, it is necessary to save eipc and eipsw. this is accomplished by the following procedure. (1) acknowledgement of maskable interrupts in servicing program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (inte rrupt acknowledgement enabled) ... ... maskable interrupt acknowledgement ... ... ? di instruction (interr upt acknowledgement disabled) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction
chapter 7 interruption/exception processing function 227 user's manual u14980ej2v1ud (2) generation of exception in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ... ? trap instruction exception such as trap instruction acknowledged. ... ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction the priority order for multiple interr upt servicing control has 8 levels, fr om 0 to 7 for each maskable interrupt request (0 is the highest priority), but it can be set as desired via software. the priority order is set using the xxprn0 to xxprn2 bits of the interr upt control request register (xxlcn), which is provided for each maskable interrupt request. after system reset, an interrupt request is masked by the xxmkn bit and the priority order is set to level 7 by the xxprn0 to xxprn2 bits. the priority order of maskable interrupts is as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been sus pended as a result of multiple servic ing control is resumed after the servicing of the higher priority interrupt has been co mpleted and the reti instru ction has been executed. a pending interrupt request is acknowledged after the cu rrent interrupt servici ng has been completed and the reti instruction has been executed. caution in a non-maskable interrupt servicing routin e (time until the reti instruction is executed), maskable interrupts are susp ended and not acknowledged. remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 )
chapter 7 interruption/exception processing function 228 user's manual u14980ej2v1ud 7.7 interrupt latency time the following table describes the v850e/m a2 interrupt latency time (from inte rrupt generation to start of interrupt servicing). figure 7-14. pipeline operation at inte rrupt request acknowledgement (outline) internal clock instruction 1 instruction 2 interrupt acknowledgement operation instruction (start instruction of interrupt servicing routine) interrupt request if id ex df wb ifx idx 4 system clocks if interleave access note if id ex int1 int2 int3 int4 note for interleave access, refer to 8.1.2 2-clock branch in the v850e1 architecture user?s manual . remark int1 to int4: interrupt acknowledgement servicing ifx: invalid instruction fetch idx: invalid instruction decode interrupt latency time (internal system clock) external interrupt internal interrupt intp0n intp1n condition minimum 4 7 + analog delay time 4 + analog delay time maximum 7 10 + analog delay time 7 + analog delay time the following cases are exceptions. ? in idle/software stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession ? access to peripheral i/o register remark n = 00, 01, 10, 11, m = 00, 01, 10
chapter 7 interruption/exception processing function 229 user's manual u14980ej2v1ud 7.8 periods in which interrupts are not acknowledged an interrupt is acknowledged while an instruction is being executed. however, no interrupt will be acknowledged between an interrupt non-sample in struction and the next instructi on (interrupt is held pending). the interrupt request non-sampling instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? store instruction for t he command register (prcmd) ? load, store, or bit manipulation inst ructions for the following registers. ? interrupt-related registers: interrupt control register (xxicn), in terrupt mask registers 0 to 3 (imr0 to imr3), in-service priority register (ispr) ? csi-related registers: clocked serial interface clock selection registers 0, 1 (csic0, csic1), clocked serial interface mode registers 0, 1 (csim0, csim1), serial i/o shift regist ers 0, 1 (sio0, sio1), re ceive-only serial i/o shift registers 0, 1 (sioe0, sioe1), clocked serial inte rface transmit buffer registers 0, 1 (sotb0, sotb1)
230 user's manual u14980ej2v1ud chapter 8 prescaler unit (prs) the prescaler divides the internal system clock and supplies the divided clock to internal peripheral units. the divided clock differs depending on the unit. for the timer units and a/d converter, a 2-division clock is used. for other units, the input clock should be selected using that unit?s control register. the cpu operates with the internal system clock.
231 user's manual u14980ej2v1ud chapter 9 clock generator function the clock generator (cg) generates and controls t he internal system clock (f xx ) that is supplied to each internal unit, such as the cpu. 9.1 features ? multiplier function using a phase locked loop (pll) synthesizer ? clock sources ? oscillation by connecting a resonator ? external clock ? power saving modes ? halt mode ? idle mode ? software stop mode ? internal system clock output function 9.2 configuration x1 x2 clock generator (cg) cksel (f x ) cpu, on-chip peripheral i/o time base counter (tbc) clkout remark f x : external resonator or external clock frequency
chapter 9 clock generator function 232 user's manual u14980ej2v1ud 9.3 input clock selection the clock generator consists of an oscillator and a pll synthesizer. for example, connecting a 4.0 mhz crystal resonator or ceramic resonator to pins x1 and x2 enables a 40 mhz internal system clock (f xx ) to be generated when the multiplier is 10. also, an external clock can be input directly to the oscillat or. in this case, the clock signal should be input only to pin x1 (pin x2 should be left open). two basic operation m odes are provided for the clock generator. these are pll mode and direct mode. the operation mode is selected by the cksel pin. the input to this pin is latched on reset. cksel operating mode 0 pll mode 1 direct mode caution the input level for the cksel pin must be fixed. if it is switched during operation, a malfunction may occur. 9.3.1 direct mode in direct mode, an external clock having twice the freque ncy of the internal system clock is input. the maximum frequency that can be input in direct mode is 40 mhz. the v850e/ma2 is mainly used in application systems which operate at relatively low frequencies. caution in direct mode, an external clock must be input (an external resonator should not be connected).
chapter 9 clock generator function 233 user's manual u14980ej2v1ud 9.3.2 pll mode in pll mode, an external resonator is connected or external clock is input and multiplied by the pll synthesizer. the multiplied pll output is divided by the division ratio s pecified by the clock control register (ckc) to generate a system clock that is 10, 5, 2. 5, or 1 times the frequency (f x ) of the external resonator or external clock. after reset, an internal system clock (f xx ) that is 1 time the frequency (1 f x ) of the internal clock frequency (f x ) is generated. when a frequency (10 f x ) that is 10 times the clock frequency (f x ) is generated, a system with low noise and low power consumption can be realized because a frequency of up to 40 mhz is obtained based on a 4 mhz external resonator or external clock. in pll mode, if the clock supply from an external resonator or external clock source stops, operation of the internal system clock (f xx ) based on the self-propelled frequency of the clock gen erator?s internal voltage controlled oscillator (vco) continues. however, do not dev ise an application method expecting to use this self-propelled frequency. example: clocks when pll mode (f xx = 10 f x ) is used system clock frequency (f xx ) external resonator or external clock frequency (f x ) 40.000 mhz 4.0000 mhz caution only an f x (4 mhz) value for which 10 f x does not exceed the system clock maximum frequency (40 mhz) can be used for the oscilla tion frequency or external clock frequency. however, if any of 5 f x , 2.5 f x , or 1 f x is used, a frequency of 4 to 6.6 mhz can be used. remark note the following when pll mode is selected (f xx = 5 f x , f xx = 2.5 f x , or f xx = 1 f x ) if the v850e/ma2 does not need to be operated at high frequency, use f xx = 5 f x , f xx = 2.5 f x , or f xx = 1 f x to reduce the power consumption by loweri ng the system clock frequency using software. 9.3.3 peripheral command register (phcmd) this is an 8-bit register that is used to set protection for writing to registers that can significantly affect the system so that the applicatio n system is not halted u nexpectedly due to erroneous program execution. this register can be written only in 8-bit units (when it is read, undefined data is read out). writing to the first specific register (ckc register) is only valid after first writing to the phcmd register. because of this, the register value can be overwr itten only with the specified sequence, preventing an illegal write operation from being performed. 7 6 5 4 3 2 1 0 address after reset phcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 fffff800h undefined bit position bit name function 7 to 0 reg7 to reg0 registration code (arbitrary 8-bit data) the specific registers targeted are as follows. ? clock control register (ckc) the generation of an illegal store oper ation can be checked with the prerr bit of the peripheral status register (phs).
chapter 9 clock generator function 234 user's manual u14980ej2v1ud 9.3.4 clock control register (ckc) the clock control register is an 8-bit register that controls the internal system clock (f xx ) in pll mode. it can be written to only by a specific sequence combination so that it cannot easily be ov erwritten by mistake due to erroneous program execution. this register can be read or written in 8-bit units. caution do not change bits ckdi v2 to ckdiv0 in direct mode. 7 6 5 4 3 2 1 0 address after reset ckc 0 0 tbcs cesel 0 ckdiv2 ckdiv1 ckdiv0 fffff822h 00h bit position bit name function 5 tbcs time base count select selects the time base counter clock. 0: f x /2 8 1: f x /2 9 for details, see 9.6.2 time base counter (tbc) . 4 cesel crystal/external select specifies the functions of the x1 and x2 pins. 0: a resonator is connected to the x1 and x2 pins 1: an external clock is connected to the x1 pin when cesel = 1, the oscillator feedback loop is disconnected to prevent current leak in software stop mode. clock divide sets the internal system clock (f xx ) when pll mode is used. ckdiv2 ckdiv1 ckdiv0 internal system clock (f xx ) 0 0 0 f x 0 0 1 2.5 f x 0 1 1 5 f x 1 1 1 10 f x other than above setting prohibited 2 to 0 ckdiv2 to ckdiv0 to change the internal system clock freque ncy in the middle of an operation, be sure to set it to f x once, and then change the frequency as desired. example clock generator settings ckc register operation mode cksel pin ckdiv2 ckdiv1 ckdiv0 input clock (f x ) internal system clock (f xx ) direct mode high-level input 0 0 0 16 mhz 8 mhz 0 0 0 4 mhz 4 mhz 0 0 1 4 mhz 10 mhz 0 1 1 4 mhz 20 mhz pll mode low-level input 1 1 1 4 mhz 40 mhz other than above setting pr ohibited setting prohibited
chapter 9 clock generator function 235 user's manual u14980ej2v1ud data is set in the clock control register (ckc) according to the following sequence. <1> disable interrupts (set the np bit of psw to 1) <2> prepare data in any one of the general-purpose registers to set in the specific register. <3> write data to the peripheral command register (phcmd) <4> set the clock control register (c kc) (with the following instructions). ? store instructions (st/sst instruction) <5> assert the nop instructions (5 instructions (<5> to <9>)) <10> release the interrupt disabled state (set the np bit of psw to 0). [sample coding] <1> ldsr rx, 5 <2> mov 0x07, r10 <3> st.b r10, phcmd [r0] <4> st.b r10, ckc [r0] <5> nop <6> nop <7> nop <8> nop <9> nop <10> ldsr ry, 5 remark rx: value written to psw ry: value returned to psw no special sequence is required to read the specific register. cautions 1. if an interrupt is ack nowledged between the issuing of data to the phcmd <3> and writing to the specific register imme diately after <4>, the write operati on to the specific register is not performed and a protection error (the prerr bi t of the phs register = 1) may occur. therefore, set the np bit of the psw to 1 <1> to disable interrupt acknowledgement. also disable interrupt acknowledgement as well when selecting a bit manipulat ion instruction for the specific register setting. 2. although the data written to the phcmd register is dummy data however, use the same register as the general-purpose register used in specific register setting <4> for writing to the phcmd register (<3>). the same met hod should be applied wh en using a general- purpose register for addressing. 3. before executing this processi ng, complete all dma transfers.
chapter 9 clock generator function 236 user's manual u14980ej2v1ud 9.3.5 peripheral status register (phs) if a write operation is not performed in the correct sequence including access to the command register for the protection-targeted internal registers, writing is not performed and a protecti on error is generated, setting the status flag (prerr) to 1. this flag is a cumula tive flag. after checking the prerr flag, it is cleared to 0 by an instruction. this register can be read or written in 8-bit or 1-bit units 7 6 5 4 3 2 1 <0> address after reset phs 0 0 0 0 0 0 0 prerr fffff802h 00h bit position bit name function 0 prerr protection error 0: protection error does not occur 1: protection error occurs the operation conditions of the prerr flag are as follows. set conditions: <1> if the operation of the relevant st ore instruction for the per ipheral i/o is not a write operation for the phcmd register, but a peri pheral specific register is written to. <2> if the first store instruction operation after the write operation to t he phcmd register is for memory other than the specific registers and peripheral i/o. reset conditions: <1> if the prerr flag of the phs register is set to 0. <2> if the system is reset
chapter 9 clock generator function 237 user's manual u14980ej2v1ud 9.4 pll lockup the lockup time (frequency stabilization time) is the time from when the power is turned on or the software stop mode is released until the phase locks at the prescribed frequen cy. the state until this stab ilization occurs is called a lockup state, and the stabilized state is called a lock state. the lock register (lockr) has a lock flag that re flects the stabilized state of the pll frequency. this register is read-only in 8-bit or 1-bit units. caution if the phase is locked, the lock flag is cleared to 0. if it is unlocked later because of a standby status, the lock flag is set to 1. if the ph ase is unlocked by a cause other than the standby status, however, the lock flag is not affected (lock = 0). 7 6 5 4 3 2 1 <0> address after reset lockr 0 0 0 0 0 0 0 lock fffff824h 0000000xb bit position bit name function 0 lock lock status flag this is a read-only flag that indicates the pll lock state. this flag holds the value 0 as long as a lockup state is maintained and is not initialized by a system reset. 0: indicates that the pll is locked. 1: indicates that the pll is not locked (unlock state). if the clock stops, the power fails, or some other factor oper ates to cause an unlock state to occur, for control processing that depends on software execution speed, such as real-time processing, be sure to judge the lock flag according to software immediately after operation begins so that processing does not begin until after the clock stabilizes. on the other hand, static proce ssing such as the setting of internal hardware or the initialization of register data or memory data can be executed without wa iting for the lock flag to be reset. the relationship between the oscillation st abilization time (the time from when t he resonator starts to oscillate until the input waveform stabilizes) when a resonator is used, an d the pll lockup time (the time until frequency stabilizes) is shown below. oscillation stabilization time < pll lockup time.
chapter 9 clock generator function 238 user's manual u14980ej2v1ud 9.5 power save control 9.5.1 overview the power save function has the following three modes. (1) halt mode in this mode, the clock generator (oscillator and pl l synthesizer) continues to operate, but the cpu's operation clock stops. since the supply of clocks to on-chip peripheral functions other than the cpu continues, operation continues. the power consumption of the overall system can be reduced by intermittent operation that is achieved due to a combinat ion of halt mode and normal operation mode. the system is switched to halt mode by a specific instruct ion (the halt instruction). (2) idle mode in this mode, the clock generator (oscillator and pll synthesizer) continues to oper ate, but the supply of internal system clocks is stopped, which causes the overall system to stop. when the system is released from idle mode, it can be switched to normal operation mode quickly because the oscillator's oscillation stabi lization time need not be secured. the system is switched to idle mode acco rding to the psmr register setting. idle mode is located midway between software stop mode and halt mode in relation to the clock stabilization time and current consumption. it is used for situations in which a low current consumption mode is to be used and the clock stabilization time is to be eliminated after the mode is released. (3) software stop mode in this mode, the overall system is stopped by stopping the cl ock generator (oscillator and pll synthesizer). the system enters an ultra-low pow er consumption state in which only leak current is lost. the system is switched to software stop mode according to a psmr register setting. (a) pll mode the system is switched to software stop mode by se tting the register according to software. the pll synthesizer's clock output is stopped at the same time that the oscillator is stopped. after software stop mode is released, the oscillator's oscillation stab ilization time must be secured until the system clock stabilizes. also, pll lockup time may be required depending on the program. when a resonator or external clock is connected, following the release of the software stop mode, execution of the program is started after the count time of the time base counter has elapsed. (b) direct mode to stop the clock, set the x1 pin to low level. after the release of software stop mode, execution of the program is started after the count-time of the time base counter has elapsed.
chapter 9 clock generator function 239 user's manual u14980ej2v1ud table 9-1 shows the operat ion of the clock gen erator in normal operation mode , halt mode, idle mode, and software stop mode. an effective low power consumption system can be r ealized by combining these modes and switching modes according to the required use. figure 9-1. power save mode state transition diagram normal operation mode software stop mode set stop mode idle mode set idle mode release according to reset, nmi, or maskable interrupt note set halt mode release according to reset, nmi, or maskable interrupt halt mode release according to reset, nmi, or maskable interrupt note note intp1n (n = 00, 01, 10) when the level detection is specified for intp 1n pin, software stop mode and idle mode cannot be released. table 9-1. clock generator oper ation using power save control clock source power save mode oscillator pll synthesizer clock supply to peripheral i/o clock supply to the cpu normal operation halt mode ? idle mode ? ? oscillation with resonator software stop mode ? ? ? ? normal operation ? halt mode ? ? idle mode ? ? ? pll mode external clock software stop mode ? ? ? ? normal operation ? ? halt mode ? ? ? idle mode ? ? ? ? direct mode external clock software stop mode ? ? ? ? remark : operating ? : stopped
chapter 9 clock generator function 240 user's manual u14980ej2v1ud 9.5.2 control registers (1) power save mode register (psmr) this is an 8-bit register that controls power save mode. it is effective only when the stb bit of the psc register is set to 1. writing to the psmr register is exec uted by the store instruction (st/sst instruction) and a bit manipulation instruction (set1/clr1 /not1 instruction). this register can be read or written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 <0> address after reset psmr 0 0 0 0 0 0 0 psm fffff820h 00h bit position bit name function 0 psm power save mode specifies idle mode or software stop mode. 0: switches the system to idle mode 1: switches the system to software stop mode (2) command register (prcmd) this is an 8-bit register that is used to set protection for write operations to regi sters that can significantly affect the system so that the appl ication system is not halted unexpe ctedly due to erroneous program execution. writing to the first specific register (pow er save control register (psc)) is only valid after first writing to the prcmd register. because of this, the r egister value can be overwritten only by the specified sequence, preventing an illegal writ e operation from being performed. this register can only be written in 8-bit uni ts. the undefined data is read out if read. 7 6 5 4 3 2 1 0 address after reset prcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 fffff1fch undefined bit position bit name function 7 to 0 reg7 to reg0 registration code (arbitrary 8-bit data) the specific register targeted is t he power save control register (psc).
chapter 9 clock generator function 241 user's manual u14980ej2v1ud (3) power save control register (psc) this is an 8-bit register that controls the power save function. this register, which is one of the specific registers, is effective only when accessed by a specific sequence duri ng a write operation. this register can be read or written in 8-bit or 1-bi t units. if bit 7 or 6 is set to 1, operation cannot be guaranteed. caution it is impossible to set stb bit and nmim or intm bit at the same time. be sure to set stb bit after setting nmim or intm bit. 7 6 <5> <4> 3 2 <1> 0 address after reset psc 0 0 nmim intm 0 0 stb 0 fffff1feh 00h bit position bit name function 5 nmim nmi mode this is the enable/disable setting bit for standby mode release using valid edge input of nmi. 0: enables nmi cancellation 1: disables nmi cancellation 4 intm int mode this is the enable/disable setting for st andby mode release using an unmasked maskable interrupt (intp1n) (n = 00, 01, 10). 0: enables maskable interrupt cancellation 1: disables maskable interrupt cancellation 1 stb stand-by mode indicates the stand-by mode status. if 1 is written to this bit, the system ent ers idle or software stop mode (using the psm bit of the psmr register). when stand-by mode is released, this bit is automatically reset to 0. 0: stand-by mode is released 1: stand-by mode is in effect data is set in the power save control regist er (psc) according to the following sequence. <1> set the power save mode register ( psmr) (with the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <2> prepare data in any one of the general-purpose registers to set to the specific register. <3> write data to the command register (prcmd). <4> set the power save control register (psc) (with the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> assert the nop instructions (5 instructions (<5> to <9>)).
chapter 9 clock generator function 242 user's manual u14980ej2v1ud [sample coding] <1> st.b r11, psmr [r0] ; set psmr register <2> mov 0 02, r10 <3> st.b r10, prcmd [r0] ; write prcmd register <4> st.b r10, psc [r0] ; set psc register <5> nop ; dummy instruction <6> nop ; dummy instruction <7> nop ; dummy instruction <8> nop ; dummy instruction <9> nop ; dummy instruction (next instruction) ; execution routine after software stop mode and idle mode release no special sequence is required to read the specific register. cautions 1. a store instruction for the command regi ster does not acknowledge in terrupts. this coding is made on assumption that <3> and <4> above are executed by the program with consecutive store instructions. if another instruction is set between <3> and <4>, the above sequence may become in effectiv e when the interrupt is ackno wledged by that instruction, and a malfunction of the program may result. 2. although the data written to the prcmd re gister is dummy data, use the same register as the general-purpose register used in specific register setting <4> for writing to the prcmd register (<3>). the same method should be applied when using a ge neral-purpose register for addressing. 3. at least 5 nop instructions must be inserted after executi ng a store instruction to the psc register to set software stop or idle mode. 4. before executing this processi ng, complete all dma transfers.
chapter 9 clock generator function 243 user's manual u14980ej2v1ud 9.5.3 halt mode (1) setting and operation status in halt mode, the clock generator (oscillator and pll synthesizer) continues to o perate, but the operation clock of the cpu is stopped. since the supply of clocks to on-chip peri pheral i/o units other than the cpu continues, operation continues. the power consumption of the overall sys tem can be reduced by setting the system to halt mode while the cpu is idle. the system is switched to halt mode by the halt instruction. although program execution stops in ha lt mode, the contents of all regist ers, internal ram, and ports are maintained in the state they were in immediately before halt mode began. also, operation continues for all on-chip peripheral i/o units (other than ports) that do not depend on cpu instructio n processing. table 9-2 shows the status of each hardware unit in halt mode. caution if the halt instruction is executed while an interrupt is being held pending, the halt mode is set once but it is immediately rele ased by the pending interrupt request. table 9-2. operation status in halt mode function operation status clock generator operating internal system clock operating cpu stopped ports maintained on-chip peripheral i/o (e xcluding ports) operating internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are maintained in the state they were in immediately before halt mode began. d0 to d15 a0 to a24 rd, we uwr, lwr ldqm, udqm cs0, cs3, cs4, cs7 sdras sdcas refrq hldak hldrq wait sdcke operating sdclk clkout clock output
chapter 9 clock generator function 244 user's manual u14980ej2v1ud (2) release of halt mode halt mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request, or reset pin input. (a) release by non-maskable interrupt request or unmasked maskable interrupt request halt mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority. however, if the system is set to halt mode during an interrupt servicing routine, operation will differ as follows. (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being serviced, halt m ode is released, but the newly ge nerated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt reques t that is currently being servic ed, halt mode is released and the newly generated interrupt request is acknowledged. table 9-3. operation after halt mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction (b) release by reset pin input this is the same as a normal reset operation.
chapter 9 clock generator function 245 user's manual u14980ej2v1ud 9.5.4 idle mode (1) setting and operation status in idle mode, the clock generator (oscillator and pll sy nthesizer) continues to oper ate, but the supply of internal system clocks is stopped which c auses the overall system to stop. when idle mode is released, the system can be s witched to normal operation mode quickly because the oscillator's oscillation stabilization time or the pll lockup time need not be secured. the system is switched to idle mode by setting the psc or psmr register using a store instruction (st or sst instruction) or a bit manipul ation instruction (set1, clr1, or not1 instruction) (refer to 9.5.2 control registers ). in idle mode, program execution is stopped, and the contents of all regi sters, internal ram, and ports are maintained in the state they were in immediately be fore execution stopped. the operation of on-chip peripheral i/o units (excluding ports) also is stopped. table 9-4 shows the status of each hardware unit in idle mode.
chapter 9 clock generator function 246 user's manual u14980ej2v1ud table 9-4. operation status in idle mode function operation status clock generator operating internal system clock stopped cpu stopped ports maintained on-chip peripheral i/o (excluding ports) stopped internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are maintained in the state they were in immediately before idle mode began. d0 to d15 a0 to a24 high impedance rd, we uwr, lwr ldqm, udqm cs0, cs3, cs4, cs7 high-level output sdras sdcas refrq operating hldak high-level output hldrq wait input (no sampling) sdcke sdclk clkout low-level output
chapter 9 clock generator function 247 user's manual u14980ej2v1ud (2) release of idle mode idle mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (intp1n), or reset pin input (n = 00, 01, 10). (a) release by non-maskable interrupt request or unmasked maskable interrupt request idle mode can be released by an interrupt request only when it has been set with the intm and nmim bits of the psc register cleared to 0. idle mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request (intp1n) regardless of t he priority. however, if the system is set to idle mode during a maskable interrupt servicing routine, operati on will differ as follows (n = 00, 01, 10). (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being serviced, idle mode is released, but the newly generated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt reques t that is currently being servic ed, idle mode is released and the newly generated interrupt request is acknowledged. table 9-5. operation after idle mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction if the system is set to idle mode during an nmi se rvicing routine, idle mode is released, but the interrupt is not acknowledged (interrupt is held pending). interrupt servicing that is started when idle mode is released by nmi pin input is handled in the same way as normal nmi interrupt servicing that occu rs during an emergency (because the nmi interrupt handler address is unique). ther efore, when a program must be able to distinguish between these two situations, a software status must be prepared in advance and that status must be set before setting the psmr register using a store instructi on or a bit manipulation instruction. by checking for this status during nmi interrupt servicing, an ordinary nmi can be distinguished from the pr ocessing that is started when idle mode is released by nmi pin input. (b) release by reset pin input this is the same as a normal reset operation.
chapter 9 clock generator function 248 user's manual u14980ej2v1ud 9.5.5 software stop mode (1) setting and operation status in software stop mode, the clock generator (oscillator and pll synthesizer) is stopp ed. the overall system is stopped, and ultra-low power consumption is achieved in which only leak current is lost. the system is switched to software st op mode by using a store instructi on (st or sst instruction) or bit manipulation instruction (set1, clr1, or not1 inst ruction) to set the psc and psmr registers (refer to 9.5.2 control registers ). when pll mode and resonator connection mode (cesel bit of ckc register = 0) ar e used, the oscillator's oscillation stabilization time must be secu red after software stop mode is released. in both pll and direct mode, following the release of software stop mode, execution of the program is started after the count time of the time base counter has elapsed. although program execution stops in software stop mode, the contents of all registers, internal ram, and ports are maintained in the state they were in i mmediately before software stop mode began. the operation of all on-chip peripheral i/o uni ts (excluding ports) is also stopped. table 9-6 shows the status of each hardware unit in software stop mode.
chapter 9 clock generator function 249 user's manual u14980ej2v1ud table 9-6. operation stat us in software stop mode function operation status clock generator stopped internal system clock stopped cpu stopped ports maintained note on-chip peripheral i/o (excluding ports) stopped internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are maintained in the state they were in immediately before software stop mode began. d0 to d15 a0 to a24 high impedance rd, we uwr, lwr ldqm, udqm cs0, cs3, cs4, cs7 high-level output sdras sdcas refrq operating hldak high-level output hldrq wait input (no sampling) sdcke sdclk clkout low-level output note when the v dd value is within the operable range. howe ver, even if it drops below the minimum operable voltage, as long as the data retention voltage v dddr is maintained, the contents of only the internal ram will be maintained.
chapter 9 clock generator function 250 user's manual u14980ej2v1ud (2) release of software stop mode software stop mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (intp1n), or reset pin input. also, to re lease software stop mode when pll mode (cksel pin = low level) and resonator connection mode (cesel bit of ckc register = 0) ar e used, the oscillator's oscillation stabilization time mu st be secured (n = 00, 01, 10). moreover, the oscillation stabilization time must be secured even when an external clock is connected (cesel bit = 1). see 9.4 pll lockup for details. (a) release by non-maskable interrupt request or unmasked maskable interrupt request software stop mode can be released by an interrupt request only when it has been set with the intm and nmim bits of the psc register cleared to 0. software stop mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request (intp1n) regardle ss of the priority. however, if the system is set to software stop mode during an interrupt servicing routine, oper ation will differ as follows (n = 00, 01, 10). (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being servicing, software stop mode is released, but the newly generated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt request that is currently being serviced, software stop mode is released and the newly generated interrupt request is acknowledged. table 9-7. operation after software stop mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction if the system is set to software stop mode during an nmi servicing routine, software stop mode is released, but the interrupt is not ackn owledged (interrupt is held pending). interrupt servicing that is start ed when software stop mode is released by nmi pin input is handled in the same way as normal nmi interrupt servicing t hat occurs during an emergency (because the nmi interrupt handler address is unique) . therefore, when a program must be able to distinguish between these two situations, a software status must be prepar ed in advance and that status must be set before setting the psmr register using a store instru ction or a bit manipulation instruction. by checking for this status during nmi interrupt servic ing, an ordinary nmi can be distinguished from the servicing that is started when software stop mode is released by nmi pin input. (b) release by reset pin input this is the same as a normal reset operation.
chapter 9 clock generator function 251 user's manual u14980ej2v1ud 9.6 securing oscillation stabilization time 9.6.1 oscillation stabilization time security specification two specification methods can be used to secure the time from when software stop mode is released until the stopped oscillator stabilizes. (1) securing the time using an on-chip time base counter software stop mode is released when a valid edge is input to the nmi pin or a maskable interrupt request is input (intp1n). if oscillation is st arted by inputting an active edge to the pin, the time base counter (tbc) starts counting, and the time until th e clock output from the oscillator stabilizes is secured during that counting time (n = 00, 01, 10). oscillation stabilization time = tbc counting time after a fixed time, internal system clock output be gins, and processing branches to the nmi interrupt or maskable interrupt (intp1n) handl er address (n = 00, 01, 10). oscillation waveform (x2) software stop mode set oscillator is stopped clkout (output) internal main clock stop state nmi (input) note time base counter counting time note valid edge: when specified as the rising edge. the nmi pin should usually be set to an inactive level (for example, high level when the valid edge is specified as the falling edge) in advance. software stop mode is immediately released by nmi valid edge input or maskable interrupt request input (intp1n) if software stop mode is set before the cp u acknowledges the interrupt (n = 00, 01, 10). if direct mode or external clock con nection mode (cesel bit of ckc regist er = 1) is used, program execution begins after the count time of the time base counter has elapsed. also, even if pll mode and resonato r connection mode (cesel bit of ckc register = 0) are used, program execution begins after the oscillation stabilization time is secured according to the time base counter, which begins counting due to nmi pin valid edge input.
chapter 9 clock generator function 252 user's manual u14980ej2v1ud (2) securing the time according to th e signal level width (reset pin input) software stop mode is released due to falling edge input to the reset pin. the time until the clock output from t he oscillator stabilizes is secured according to the low level width of the signal that is input to the pin. the supply of internal system clocks be gins after a rising edge is input to the reset pin, and processing branches to the handler addr ess used for a system reset. oscillation waveform (x2) software stop mode set oscillator is stopped internal main clock stop state internal system reset signal oscillation stabilization time secured by reset reset (input) undefined clkout (output) undefined
chapter 9 clock generator function 253 user's manual u14980ej2v1ud 9.6.2 time base counter (tbc) the time base counter (tbc) is used to secure the osci llator's oscillation stabilization time when software stop mode is released. when an external clock is connected (cesel bit of ckc regi ster = 1) or a resonator is connected (pll mode and cesel bit of ckc register = 0), the tbc counts the o scillation stabilization time after software stop mode is released, and program execution begi ns after the count is completed. the tbc count clock is selected according to the tbcs bi t of the ckc register, and the next counting time can be set (reference). table 9-8. counting time examples (f xx = 10 f x ) counting time f x = 4.0000 mhz tbcs bit count clock f xx = 40.000 mhz 0 f x /2 8 16.3 ms 1 f x /2 9 32.6 ms f x : external oscillation frequency f xx : internal system clock
254 user's manual u14980ej2v1ud chapter 10 timer/counter function (real-time pulse unit) 10.1 timer c 10.1.1 features (timer c) timer c is a 16-bit timer/counter t hat can perform the following operations. ? interval timer function ? pwm output ? external signal cycle measurement 10.1.2 function overview (timer c) ? 16-bit timer/counter ? capture/compare common registers: 4 ? interrupt request sources ? capture/match interrupt requests: 4 ? overflow interrupt requests: 2 ? timer/counter count clock sources: 2 (selection of external pulse input or internal system clock division) ? either free-running mode or overflow stop mode can be selected as the operation mode when the timer/counter overflows ? timer/counter can be cleared by a match of the timer/counter and a compare register ? external pulse outputs: 1
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 255 10.1.3 basic configuration of timer c table 10-1. timer c configuration timer count clock register read/write generated interrupt signal capture trigger timer output s/r other functions tmc0 read intov00 ? ? ? ccc00 read/write intm000 intp000 to00 (s) a/d conversion start trigger ccc01 read/write intm001 intp001 to00 (r) a/d conversion start trigger tmc1 read intov01 ? ? ? ccc10 read/write intm010 intp010 ? a/d conversion start trigger timer c f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512, ccc11 read/write intm011 intp011 ? a/d conversion start trigger remarks f xx : internal system clock s/r: set/reset (1) timer c (16-bit timer/counter) r note q sq tmcn (16 bits) cccn0 cccn1 intov0n intm0n0 intp0n1 f xx m/2 f xx m/4 f xx m/8 f xx m/16 f xx m/32 f xx m/64 f xx m/128 f xx m/256 f xx /2 ti0n0/intp0n0 intm0n1 to0n clear & start selector selector f xx m note reset priority remarks 1. n = 0, 1 2. f xx : internal system clock
chapter 10 timer/counter function (real-time pulse unit) 256 user's manual u14980ej2v1ud 10.1.4 timer c (1) timers c0, c1 (tmc0, tmc1) tmcn functions as a 16-bit free-running timer or as an event counter for an external signal. besides being mainly used for cycle measurement, tmcn c an be used as pulse output (n = 0, 1). tmcn is read-only in 16-bit units. cautions 1. the tmcn register can only be read. if writing is performed to the tmcn register, the subsequent operation is undefined. 2. if the tmccaen bit of the tmccn0 regist er is cleared (0), a reset is performed asynchronously. tmc1 fffff610h 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tmc0 fffff600h 0000h address after reset 0 tmcn performs the count-up operations of an internal count clock or external count clock. timer starting and stopping are controlled by the tmccen bit of timer m ode control register cn0 (tmccn0) (n = 0, 1). the internal or external count clock is selected by the etin bit of timer mode control register cn1 (tmccn1) (n = 0, 1). (a) selection of the external count clock tmcn operates as an event counter. when the eti bit of timer mode control register cn1 (tm ccn1) is set (1), tmcn counts the valid edges of the external clock input (ti0n0), synchronized with th e internal count clock. the valid edge is specified by valid edge selection regist er cn (sescn) (n = 0, 1). caution when the intp0n0/ti0n0 pin is used as ti0n0, disable the intp0n0 interrupt or set cccn0 to compare mode (n = 0, 1).
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 257 (b) selection of the internal count clock tmcn operates as a free-running timer. when an internal clock is specified as a count clo ck by timer mode control register cn1 (tmccn1), tmcn is counted up for each input clock cycle s pecified by the csn0 to csn2 bits of the tmccn0 register (n = 0, 1). a division by the prescaler can be selected for the count clock from among f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, and f xx /512 by the tmccn0 register (f xx : internal system clock). an overflow interrupt can be generated if the timer overflows. also, the timer can be stopped following an overflow by setting the ostn bit of the tmccn1 register to 1. caution the count clock cannot be ch anged while the timer is operating. the conditions when the tmcn register becomes 0000h are shown below. (a) asynchronous reset ? tmccaen bit of tmccn0 register = 0 ? reset input (b) synchronous reset ? tmccen bit of tmccn0 register = 0 ? the cccn0 register is used as a compare regist er, and the tmcn and cccn0 registers match when clearing the tmcn register is enabled (c clrn bit of the tmccn1 register = 1)
chapter 10 timer/counter function (real-time pulse unit) 258 user's manual u14980ej2v1ud (2) capture/compare registers cn0 a nd cn1 (cccn0 and cccn1) (n = 0, 1) these capture/compare registers (cn0 and cn1) are 16-bit registers. they can be used as capture registers or compar e registers according to the cmsn0 and cmsn1 bit specifications of timer mode control register cn1 (tmccn1) (n = 0, 1). these registers can be read or written in 16-bit units. (however, write operations can only be performed in compare mode.) ccc1n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ccc0n fffff602h, fffff604h fffff612h, fffff614h 0000h 0000h address after reset 0 remark n = 0, 1 (a) setting these registers to capture regi sters (cmsn0 and cmsn1 of tmccn1 = 0) when these registers are set to capt ure registers, the valid edges of t he corresponding external interrupt signals intp0n0 and intp0n1 are detected as capture triggers. the timer tmcn is synchronized with the capture trigger, and the value of tmcn is latched in the cccn0 and cccn1 registers (capture operation). the valid edge of the intp0n0 pin is specified (risi ng, falling, or both edges) according to the ies0n01 and ies0n00 bits of the sescn register, and the valid edge of the intp0n1 pin is specified according to the ies0n11 and i es0n10 bits of the sescn register (n = 0, 1). the capture operation is performed asyn chronously relative to the count clock. the latched value is held in the capture register until the next ti me the capture operation is performed. when the tmccaen bit of timer mode control register cn0 (tmccn0) is 0, 0000h is read (n = 0, 1). if these registers are specified as capture registers, an interrupt is generated by detecting the valid edge of signals intp0n0 and intp0n1 (n = 0, 1). caution if the capture operation conflicts with th e timing of disabling the tmcn register from counting (when the tmccen bit of the tm ccn0 register = 0), the captured data becomes undefined. in addition, the intm0n 0 and intm0n1 interrupts do not occur (n = 0, 1).
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 259 (b) setting these registers to compare regi sters (cmsn0 and cmsn1 of tmccn1 = 1) when these registers are set to compare registers, t he tmcn and register values are compared for each count clock, and an interrupt is generated by a match. if the cclrn bit of timer mode control register cn1 (tmccn1) is set (1), the tmcn value is cleared (0) at the same time as a match with the cccn0 register (it is not cleared (0) by a match with the cccn1 register) (n = 0, 1). a compare register (ccc00, ccc01) is equipped with a set/reset function. the timer output (to00) is set or reset, synchronized with the generation of a match signal. the interrupt selection source differs accord ing to the function of the selected register. cautions 1. to write to capture /compare registers cn0 and cn1, always set the tmccaen bit to 1 first. if the tmccaen bit is 0, the data that is wri tten will be invalid. 2. perform a write operation to capture/c ompare registers cn0 and cn1 after setting them to compare registers according to the tmccn0 and tmccn1 registers setting. if they are set to capture registers (cmsn0 and cmsn1 bits of tmccn1 register = 0), no data is writ ten even if a write operation is performed to cccn0 and cccn1. 3. when these registers are set to compare registers, in tp0n0 and intp0n1 cannot be used (n = 0, 1).
chapter 10 timer/counter function (real-time pulse unit) 260 user's manual u14980ej2v1ud 10.1.5 timer c control registers (1) timer mode control registers c00, c10 (tmcc00, tmcc10) the tmccn0 registers control the oper ation of tmcn (n = 0, 1). these registers can be read or wr itten in 8-bit or 1-bit units. be sure to set bits 3 and 2 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. the tmccaen and other bits cannot be set at the same time. the other bits and the registers of the other tmcn unit should alw ays be set after the tmccaen bit has been set. also, to use external pins related to the timer function when timer c is used, be sure to set (1) the tmccaen bit after set ting the external pins to control mode. 2. when conflict occurs be tween an overflow and a tmccn0 register write, the ovfn bit value becomes the value written during th e tmccn0 register write (n = 0, 1). (1/2) <7> 6 5 4 3 2 <1> <0> address after reset tmcc00 ovf0 cs02 cs01 cs00 0 0 tmcce0 tmccae0 fffff606h 00h tmcc10 ovf1 cs12 cs11 cs10 0 0 tmcce1 tmccae1 fffff616h 00h bit position bit name function 7 ovfn (n = 0, 1) overflow this is a flag that indicates tmcn overflow (n = 0, 1). 0: no overflow occurs 1: overflow occurs when tmcn has counted up from ffffh to 0000h, the ovfn bit becomes 1 and an overflow interrupt request (intovf) is generated at the same time. however, if tmcn is cleared to 0000h after a match at ffffh when the cccn0 register is set to compare mode (cmsn0 bit of tmccn1 register = 1) and clearing is enabled for a match when tmcn and cccn0 are compared (cclrn bit of tmccn1 register = 1), then tmcn is considered to be cleared and the ovfn bit does not become 1. also, no intovf interrupt is generated. the ovfn bit retains the value 1 until 0 is written directly or until an asynchronous reset is performed because the tmccaen bit is 0. an interrupt operation due to an overflow is independent of the ovfn bit, and the interrupt request flag (ovifn) for intov0n is not affected even if the ov fn bit is manipulated. if an overflow occurs while the ovfn bit is being read, the flag value changes, and the change is reflected when the next read operation occurs.
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 261 (2/2) bit position bit name function count enable select selects the tmcn internal count clock (n = 0, 1). csn2 csn1 csn0 count cycle 0 0 0 f xx /4 0 0 1 f xx /8 0 1 0 f xx /16 0 1 1 f xx /32 1 0 0 f xx /64 1 0 1 f xx /128 1 1 0 f xx /256 1 1 1 f xx /512 6 to 4 csn2 to csn0 (n = 0, 1) caution the csn2 to csn0 bits must not be changed during timer operation. if they are to be changed, they must be changed after setting the tmccen bit to 0. if these bits are overwritten during timer operation, operation cannot be guaranteed. remark f xx : internal system clock 1 tmccen (n = 0, 1) count enable controls the operation of tmcn (n = 0, 1). 0: count disable (stops at 0000h and does not operate) 1: counting operation is performed caution when tmcce0 = 0, the external pulse outputs (to00) go to inactive level (the active level of to00 output is set by the actlv0 bit of the tmcc01 register). 0 tmccaen (n = 0, 1) clock action enable controls the internal count clock (n = 0, 1). 0: the entire tmcn unit is asynchronously reset. the supply of clocks to the tmcn unit stops. 1: clocks are supplied to the tmcn unit cautions 1. when the tmccaen bit is set to 0, the tmcn unit can be asynchronously reset. 2. when tmccaen = 0, the tmcn unit is in a reset state. therefore, to operate tmcn, the tmccaen bit must be set to 1. 3. when the tmccaen bit is changed from 1 to 0, all registers of the tmcn unit are initialized. when the tmccaen is set to 1 again, the tmcn unit registers must be set again.
chapter 10 timer/counter function (real-time pulse unit) 262 user's manual u14980ej2v1ud (2) timer mode control registers c01, c11 (tmcc01, tmcc11) the tmccn1 registers control the oper ation of tmcn (n = 0, 1). these registers can be read or written in 8-bit units. be sure to set bit 2 of the tmcc01 register and bits 6 and 2 of the tmcc11 register to 0, and bit 5 of the tmcc11 register to 1. if they are set to other values, the operation is not guaranteed. cautions 1. the various bits of the tmccn1 register must not be changed dur ing timer operation. if they are to be changed, th ey must be changed after setting the tmccen bit of the tmccn0 register to 0. if these bits are overwritten durin g timer operation, operation cannot be guaranteed (n = 0, 1). 2. if the ent01 and actlv0 bits are change d at the same time, a glitch (spike-shaped noise) may be generated in the to00 pin outpu t. either create a circuit configuration that will not malfunction even if a glitch is generated or make sure that the ent01 and actlv0 bits do not change at the same time (n = 0, 1). 3. to00 output is not changed by an external interrupt signal (intp0n0 or intp0n1). to use the to00 signal, specify th at the capture/compare regi sters are compare registers (cmsn0 and cmsn1 bits of tmccn1 register = 1) (n = 0, 1). (1/2) 7 6 5 4 3 2 1 0 address after reset tmcc01 ost0 ent01 actlv0 eti0 cclr0 0 cms01 cms00 fffff608h 20h tmcc11 ost1 0 1 eti1 cclr1 0 cms11 cms10 fffff618h 20h bit position bit name function 7 ostn (n = 0, 1) overflow stop sets the operation when tmcn has overflowed (n = 0, 1). 0: after the overflow, co unting continues (free running mode) 1: after the overflow, the timer ma intains the value 0000h, and counting stops (overflow stop mode). at this time, the tmccen bit of tmccn0 remains at 1. counting is restarted by a write operation to the tmccen bit. 6 ent01 enable to pin external pulse output is enabled/disabled (to00). 0: external pulse output is disabled. output of the actlv0 bit inactive level to the to00 pin is fixed. the to00 pin level is not changed even if a match signal from the compare register (ccc00, ccc01) is generated. 1: external pulse output is enabled. a compare register match causes to00 output to change. however, if capture mode is set, to00 output does not change. an actlv0 bit inactive level is output from the time when timer output is enabled until a match signal is first generated. caution if either ccc00 or ccc01 is specified as a capture register, the ent01 bit must be set to 0.
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 263 (2/2) bit position bit name function 5 actlv0 active level specifies the active level for external pulse output (to00). 0: active level is low level 1: active level is high level caution the initial value of the actlv0 bit is 1. 4 etin (n = 0, 1) external input specifies a switch between the external and internal count clock. 0: specifies the input clock (int ernal). the count clock can be selected according to the csn2 to scn0 bits of tmccn0 (n = 0, 1). 1: specifies the external clock (ti0n0). the valid edge can be selected according to the tesn1 and tesn0 bit specifications of sescn (n = 0, 1). 3 cclrn (n = 0, 1) compare clear enable sets whether the clearing of tmcn is enabled or disabled during a compare operation (n = 0, 1). 0: clearing is disabled 1: clearing is enabled (if cccn0 and tmcn match during a compare operation, tmcn is cleared). 1 cmsn1 (n = 0, 1) capture/compare mode select selects the operation mode of the capture/compare register (cccn1) (n = 0, 1). 0: the register operates as a capture register 1: the register operates as a compare register 0 cmsn0 (n = 0, 1) capture/compare mode select selects the operation mode of the capture/compare register (cccn0) (n = 0, 1). 0: the register operates as a capture register 1: the register operates as a compare register remarks 1. a reset takes precedence for t he flip-flop of the to00 output. 2. when the a/d converter is set to timer trigger m ode, the match interrupt of the compare registers becomes a start trigger for a/d conversion, and th e conversion operation begins. at this time, the compare register match interrupt also functions as a compare register match interrupt for the cpu. to prevent the generation of a compare register match in terrupt for the cpu, disable an interrupt by the interrupt mask bits (p00mk0, p00mk1, p01mk0, and p01mk1) of the interrupt control registers (p00ic0, p00ic1, p01ic0, and p01ic1).
chapter 10 timer/counter function (real-time pulse unit) 264 user's manual u14980ej2v1ud (3) valid edge selection regi sters c0, c1 (sesc0, sesc1) these registers specify the valid edge of an exte rnal interrupt request (intp000, intp001, intp010, intp011) from an external pin. the rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin. each of these registers can be read or written in 8-bit units. be sure to set bits 5 and 4 to 0. if they are set to 1, the operation is not guaranteed. caution the various bits of the sescn register must not be changed during timer operation. if they are to be changed, they must be changed after setting the tmccen bit of the tmccn0 register to 0. if the sescn register is ov erwritten during timer ope ration, operation cannot be guaranteed. 7 6 5 4 3 2 1 0 address after reset sesc0 tes01 tes00 0 0 ies0011 ies0010 ies0001 ies0000 fffff609h 00h 7 6 5 4 3 2 1 0 address after reset sesc1 tes11 tes10 0 0 ies0111 ies0110 ies0101 ies0100 fffff619h 00h bit position bit name function 7, 6 tesn1, tesn0 (n = 0, 1) edge select specifies the valid edge of the intpn pin and ti000 and ti010 pins. xesn1 xesn0 operation 0 0 falling edge 3, 2 iesn1, iesn0 (n = 001, 011) 0 1 rising edge 1 0 rfu (reserved) 1 1 both edges 1, 0 iesn1, iesn0 (n = 000, 010) ti010 tclr1 intp011 intp010 ti000 intp001 intp000
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 265 10.1.6 timer c operation (1) count operation timer c can function as a 16-bit free-running timer or as an external signal event counter. the setting for the type of operation is specified by ti mer mode control registers cn0 and cn1 (tmccn0 and tmccn1) (n = 0, 1). when it operates as a free-running timer, if the ccc0 0 or ccc01 register and the tmc0 count value match, an interrupt signal is generated and the timer output sig nal (to00) can be set or reset. also, a capture operation that holds the tmcn count value in the cccn 0 or cccn1 register is performed, synchronized with the valid edge that was detected from the external interrupt request input pin as an external trigger. the capture value is held until the nex t capture trigger is generated. caution when using intp0n0/ti0n0 pi n as an external clock input pin (t i0n0), be sure to disable the intp0n0 interrupt or set the cccn0 regi ster to compare mode (n = 0, 1). figure 10-1. basic operation of timer c 0001h 0000h 0002h 0003h fbfeh fbffh 0001h 0002h 0000h tmcn count clock ? count disabled tmccen 0 ? count start tmccen 1 ? count start tmccen 1 remark n = 0 , 1
chapter 10 timer/counter function (real-time pulse unit) 266 user's manual u14980ej2v1ud (2) overflow when the tmcn register has counted the count clock from ffffh to 0000h, the ovfn bit of the tmccn0 register is set (1), and an overflow interrupt (intov0n) is generated at the same time. however, if the cccn0 register is set to compare mode (cmsn0 bit = 1) and to the value ffffh when match clearing is enabled (cclrn bit = 1), then the tmcn register is considered to be cleared and the ovfn bit is not set (1) when the tmcn register changes fr om ffffh to 0000h. also, the over flow interrupt (intov0n) is not generated . when the tmcn register is changed from ffffh to 000 0h because the tmccen bit changes from 1 to 0, the tmcn register is considered to be cleared, but the ovfn bit is not set (1) and no intov0n interrupt is generated. also, timer operation can be stopped after an overflow by setting the ostn bit of the tmccn1 register to 1. when the timer is stopped due to an over flow, the count operation is not re started until the tmccen bit of the tmccn0 register is set (1). operation is not affected even if the tmcce n bit is set (1) during a count operation. remark n = 0, 1 figure 10-2. operation after overflow (when ostn = 1) overflow count start overflow ffffh ffffh tmcn 0 intov0n ostn 1 tmccen 1 tmccen 1 remark n = 0, 1
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 267 (3) capture operation the tmcn register has two capture/compare regist ers. these are the cccn0 register and the cccn1 register. a capture operation or a compare operation is performed according to the settings of both the cmsn1 and cmsn0 bits of the tmccn1 register. if t he cmsn1 and cmsn0 bits of the tmccn1 register are set to 0, the register oper ates as a capture register. a capture operation that capt ures and holds the tmcn count value asynchronously relative to the count clock is performed synchronized with an external trigger. the valid edge that is detected from an external interrupt request input pin (intp0n0 or intp0n1) is used as an external trigger (capture trigger). the tmcn count value during counting is captured and held in the c apture register, synchronized with that capture trigger signal. the capture register value is hel d until the next capture trigger is generated. also, an interrupt request (intm0n0 or intm0n1) is generated by intp0n0 or intp0n1 signal input. the valid edge of the capture trigger is set by valid edge selection register cn (sescn). if both the rising and falling edges are set as capture tr iggers, the input pulse width from an external source can be measured. also, if only one of the edges is set as the capture trigger, the input pulse cycle can be measured. remark n = 0, 1 figure 10-3. capture operation example tmc1 0 tmcce1 intp011 ccc11 (capture register) n n (capture trigger) (capture trigger) remarks 1. when the tmccen bit is 0, no capture oper ation is performed even if intp011 is input. 2. valid edge of intp011: rising edge
chapter 10 timer/counter function (real-time pulse unit) 268 user's manual u14980ej2v1ud figure 10-4. tmc1 capture operation e xample (when both edges are specified) tmc1 ? count start tmcce1 1 ? overflow ovf1 1 d0 d1 d2 d0 d1 d2 interrupt request (intp011) (tmc1 count values) capture register (ccc11) remark d0 to d2: tm c1 count values
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 269 (4) compare operation the tmcn register has two capture/compare regist ers. these are the cccn0 register and the cccn1 register. a capture operation or a compare operation is performed according to the settings of both the cmsn1 and cmsn0 bits of the tmccn1 register. if 1 is set in the cmsn1 and cmsn0 bits of the tmccn1 register, the register operat es as a compare register. a compare operation that compares t he value that was set in the compare register and the tmcn count value is performed. if the tmcn count value matches the value of the compare register, which had been set in advance, a match signal is sent to the output controller. the match signal causes the timer output pin (to00) to change (timer c0 only) and an interrupt request signal (intm0n0 or intm0n1) to be generated at the same time. if the cccn0 or cccn1 regist er is set to 0000h, the 0000h after the tmcn regist er counts up from ffffh to 0000h is judged as a match. in this case, the value of the tmcn register is clear ed (set to 0) at the next counting. however, a judgment as to whether the tmcn register valu e matches 0000h is not made. the 0000h when the tmcn register begins counting is not judged as a match, either. if match clearing is enabled (cclrn bit = 1) for the cccn0 register, the tmcn register is cleared when a match with the tmcn register o ccurs during a compare operation. remark n = 0, 1 figure 10-5. compare op eration example (1/2) (a) when cclr0 = 1 and ccc00 is other than 0000h 0001h tmc0 count up 0000h n n n ? 1 compare register (ccc00) match detection (intm000) to00 pin remarks 1. the match is detected immediately after the count-up, and the match detection signal is generated. 2. n 0000h
chapter 10 timer/counter function (real-time pulse unit) 270 user's manual u14980ej2v1ud figure 10-5. compare op eration example (2/2) (b) when cclr0 = 1 and ccc00 is 0000h 0001h 0000h 0000h 0000h ffffh tmc0 intov00 count-up compare register (ccc00) match detection (intm000) to00 pin remark the match is detected immediately after the count-up, and the match detection signal is generated.
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 271 (5) external pulse output timer c has one timer output pin (to00). an external pulse output (to00) is generated w hen a match of the two compare registers (ccc00 and ccc01) and the tmc0 register is detected. if a match is detected when the tmc0 count value an d the ccc00 value are compared, the output level of the to00 pin is set. also, if a match is detect ed when the tmc0 count value and the ccc01 value are compared, the output level of the to00 pin is reset. the output level of the to00 pin can be specified by the tmcc01 register. table 10-2. to00 output control to00 output ent01 actlv0 external pulse output output level 0 0 disabled high level 0 1 disabled low level 1 0 enabled when the ccc00 register is matched: low level when the ccc01 register is matched: high level 1 1 enabled when the ccc00 register is matched: high level when the ccc01 register is matched: low level figure 10-6. tmc0 compare operati on example (set/reset output mode) tmc0 count value 0 ffffh ? count start tmcce0 1 ? overflow ovf0 1 ? overflow ovf0 1 ccc01 ccc00 ffffh ccc01 ccc00 ccc00 interrupt request (intm000) interrupt request (intm001) to00 pin ent01 1 actlv0 1
chapter 10 timer/counter function (real-time pulse unit) 272 user's manual u14980ej2v1ud 10.1.7 application examples (timer c) (1) interval timer by setting the tmccn0 and tmccn1 registers as shown in figure 10-7, timer c operates as an interval timer that repeatedly generates in terrupt requests with the value that was set in advance in the cccn0 register as the interval. when the counter value of the tmcn register matches the setting value of the cccn0 register, the tmcn register is cleared (0000h) and an interrupt request signa l (intm0n0) is generated at the same time that the count operation resumes. remark n = 0, 1 figure 10-7. contents of register settings when timer c is used as interval timer supply input clocks to internal units enable count operation 0 0/1 note 0/1 note 0/1 1 0 note 0/1 1 ostn ent01 actlv0 etin cclrn cmsn1 cmsn0 0/1 0/1 0/1 0/1 0 note 0 note 11 ovfn tmccn0 tmccn1 csn2 csn1 csn0 tmccen tmccaen use cccn0 register as compare register clear tmcn register due to match with cccn0 register continue counting after tmcn register overflows note be sure to set bits 3 and 2 of the tmccn0 regist er, bit 2 of the tmccn1 register, and bit 6 of the tmcc11 register to 0, and bit 5 of the tmcc11 regist er to 1. if they are set to other values, the operation is not guaranteed (n = 0, 1). remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0, 1
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 273 figure 10-8. interval time r operation timing example count start 0001h 0000h 0001h 0000h 0001h p pp pp pp 0000h interval time interval time interval time count clock t tmcn register cccn0 register intm0n0 interrupt clear clear remarks 1. p: setting value of cccn0 register (0000h to ffffh) t: count clock cycle interval time = (p + 1) t 2. n = 0, 1
chapter 10 timer/counter function (real-time pulse unit) 274 user's manual u14980ej2v1ud (2) pwm output by setting the tmcc00 and tmcc01 registers as shown in figure 10-9, timer c can output a pwm signal whose frequency is determined according to the setting of the cs02 to cs00 bits of the tmcc00 register, with the values that were preset in the ccc00 and ccc01 registers as the interval. when the counter value of the tmc0 register matches the setting value of the ccc00 register, the to00 output becomes active. then, when the counter value of the tmc0 register matches the setting value of the ccc01 register, the to00 output becomes inactive. the tmc0 register contin ues counting. when it overflows, its count value is cleared to 0000h, and the re gister continues counting. in this way, a pwm signal whose frequency is determined according to the setting of the cs02 to cs00 bits of the tmcc00 register can be output. when the setting value of the ccc00 register and the setting value of the ccc01 register are the same, the to00 output remains inactive and does not change. the active level of to00 output can be set by the actlv0 bit of the tmcc01 register. figure 10-9. contents of register settings when timer c is used for pwm output supply input clocks to internal units enable count operation 0 1 0/1 0/1 0 0 note 11 ost0 ent01 actlv0 eti0 cclr0 cms01 cms00 0/1 0/1 0/1 0/1 0 note 0 note 11 ovf0 tmcc00 tmcc01 cs02 cs01 cs00 tmcce0 tmccae0 use ccc00 register as compare register use ccc01 register as compare register disable clearing of tmc0 register due to match with ccc00 register enable external pulse output (to00) continue counting after tmc0 register overflows note be sure to set bits 3 and 2 of the tmcc00 register and bit 2 of the tmcc01 register to 0. if they are set to 1, the operation is not guaranteed. remark 0/1: set to 0 or 1 as necessary
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 275 figure 10-10. pwm output timing example count start clear 0001h 0000h 0001h 0000h ffffh p ppp p p qqq q q qq p count clock tmc0 register ccc00 register ccc01 register intm000 interrupt intm001 interrupt to00 (output) t remarks 1. p: setting value of ccc00 register (0000h to ffffh) q: setting value of ccc0 1 register (0000h to ffffh) p q t: count clock cycle pwm cycle = 65,536 t q ? p 65,536 2. in this example, the active level of to00 output is set to high level. duty =
chapter 10 timer/counter function (real-time pulse unit) 276 user's manual u14980ej2v1ud (3) cycle measurement by setting the tmccn0 and tmccn1 registers as shown in figure 10-11, timer c can measure the cycle of signals input to the intp0n0 pin or intp0n1 pin. the valid edge of the intp0n0 pin is selected accord ing to the ies0n01 and ies0n00 bits of the sescn register, and the valid edge of the intp0n1 pin is select ed according to the ies0n11 and ies0n10 bits of the sescn register. either the rising edge, the falling edge, or both edges can be selected as the valid edges of both pins. if the cccn0 register is set to a capt ure register, the valid edge input of t he intp0n0 pin is set as the trigger for capturing the tmcn register value in the cccn0 register. when this value is captured, an intm0n0 interrupt is generated. similarly, if the cccn1 register is set to a capture re gister, the valid edge input of the intp0n1 pin is set as the trigger for capturing the tmcn register value in the cccn1 register. when this value is captured, an intm0n1 interrupt is generated. the cycle of signals input to the intp0n0 pin is calc ulated by obtaining the difference between the tmcn register?s count value (dx) that was captured in the cccn0 register accord ing to the x-th valid edge input of the intp0n0 pin and the tmcn regist er?s count value (d(x+1)) that wa s captured in the cccn0 register according to the (x+1)-th valid edge input of the intp0n0 pin and multiplying the value of this difference by the cycle of the clock control signal. the cycle of signals input to the intp0n1 pin is calc ulated by obtaining the difference between the tmcn register?s count value (dx) that was captured in the cccn1 register accord ing to the x-th valid edge input of the intp0n1 pin and the tmcn regist er?s count value (d(x+1)) that wa s captured in the cccn1 register according to the (x+1)-th valid edge input of the intp0n1 pin and multiplying the value of this difference by the cycle of the clock control signal. remark n = 0, 1
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 277 figure 10-11. contents of register settings when timer c is used for cycle measurement supply input clocks to internal units enable count operation 0 0/1 note 0/1 note 0/1 0/1 0 note 00 ostn ent01 actlv0 etin cclrn cmsn1 cmsn0 0/1 0/1 0/1 0/1 0 note 0 note 11 ovfn tmccn0 tmccn1 csn2 csn1 csn0 tmccen tmccaen use cccn0 register as capture register (when measuring the cycle of intp0n0 input) use cccn1 register as capture register (when measuring the cycle of intp0n1 input) continue counting after tmcn register overflows note be sure to set bits 3 and 2 of the tmccn0 regist er, bit 2 of the tmccn1 register, and bit 6 of the tmcc11 register to 0, and bit 5 of the tmcc11 regist er to 1. if they are set to other values, the operation is not guaranteed (n = 0, 1). remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0, 1
chapter 10 timer/counter function (real-time pulse unit) 278 user's manual u14980ej2v1ud figure 10-12. cycle measurement operation timing example t 0001h 0000h 0001h 0000h ffffh d0 d1 d2 d3 d3 d2 d1 d0 (d1 ? d0) t (d3 ? d2) t {(10000h ? d1) + d2} t note count clock tmcn register intp0n0 (input) cccn0 register intm0n0 interrupt intov0n interrupt no overflow overflow occurs no overflow clear count start note an overflow is generated once. remarks 1. d0 to d3: tmcn register count values t: count clock cycle 2. in this example, the valid edge of intp0n0 input has been set to both edges (rising and falling). 3. n = 0, 1
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 279 10.1.8 precautions (timer c) various precautions concerning timer c are shown below. (1) if a conflict occurs between the reading of the cccn0 register and a capture operation when the cccn0 register is used in capture mode, an external trigger (intp0n0) valid edge is detected and an external interrupt request signal (intm0n0) is generated however, timer value is not stored in the cccn0 register. (2) if a conflict occurs between the reading of the cccn1 register and a capture operation when the cccn1 register is used in capture mode, an external trigger (intp0n1) valid edge is detected and an external interrupt request signal (intm0n1) is generated however, the timer value is not stored in the cccn0 register. (3) the following registers must not be re written during operation (tmccen = 1). ? csn2 to csn0 bits of tmccn0 register ? tmccn1 register ? sescn register (4) the tmccaen bit of the tmccn0 register is a tmcn reset signal. to use tmcn , first set (1) the tmccaen bit. (5) the analog noise elimination time + two cycles of the input clock are required to detect a valid edge of the external interrupt request signal (intp0n0 or intp0n1) or the external clock input (ti0n0). t herefore, edge detection will not be performed normally for changes that are less than the analog noise elimination time + two cycles of the input clock. for the analog noise elimination, refer to 7.3.8 noise elimination . (6) the operation of an external interrupt request sign al (intm0n0 or intm0n1) is automatically determined according to the operating state of the capture/compare register. when th e capture/compare register is used for a capture operation, the external interrupt reques t signal is used for valid edge detection. when the capture/compare register is used for a compare operation, the external in terrupt request signal is used for a match interrupt indicating a match with the tmcn register. (7) if the ent01 and actlv0 bits are changed at the same time, a glitch (spike shaped noise) may be generated in the to00 pin output. either create a circui t configuration that will not ma lfunction even if a glitch is generated or make sure that the ent01 and actlv0 bits do not change at the same time. remark n = 0, 1
chapter 10 timer/counter function (real-time pulse unit) 280 user's manual u14980ej2v1ud 10.2 timer d 10.2.1 features (timer d) timer d functions as a 16-bit interval timer. 10.2.2 function overview (timer d) ? 16-bit interval timer ? compare registers: 4 ? interrupt request sources: 4 sources ? count clock selected from divisions of internal system clock 10.2.3 basic configuration of timer d table 10-3. timer d configuration timer count clock register read/write generated interrupt signal capture trigger timer output s/r other functions tmd0 read ? ? ? ? cmd0 read/write intcmd0 ? ? ? tmd1 read ? ? ? ? cmd1 read/write intcmd1 ? ? ? tmd2 read ? ? ? ? cmd2 read/write intcmd2 ? ? ? tmd3 read ? ? ? ? timer d f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512 cmd3 read/write intcmd3 ? ? ? remark f xx : internal system clock s/r: set/reset (1) timer d (16-bit timer/counter) tmdn (16 bits) cmdn intcmdn f xx m/2 f xx m/4 f xx m/8 f xx m/16 f xx m/32 f xx m/64 f xx m/128 f xx m/256 f xx /2 clear & start f xx m remarks 1. n = 0 to 3 2. f xx : internal system clock
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 281 10.2.4 timer d (1) timers d0 to d3 (tmd0 to tmd3) tmdn is a 16-bit timer. it is mainly used as an interval timer for software (n = 0 to 3). starting and stopping tmdn is controlle d by the tmdcen bit of the timer mode control register dn (tmcdn) (n = 0 to 3). a division by the prescaler can be sele cted for the count clock from among f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, and f xx /512 by the csn0 to csn2 bits of the tmcdn register (f xx : internal system clock). tmdn is read-only in 16-bit units. tmd1 fffff550h 0000h tmd2 fffff560h 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tmd0 fffff540h 0000h address after reset 0 tmd3 fffff570h 0000h the conditions for which the tmdn register becomes 0000h are shown below (n = 0 to 3). ? reset input ? tmdcaen bit = 0 ? tmdcen bit = 0 ? match of tmdn register and cmdn register ? overflow cautions 1. if the tmdcaen bit of the tmcdn re gister is cleared (0), a reset is performed asynchronously. 2. if the tmdcen bit of the tmcdn register is cleared (0), a reset is performed, synchronized with the internal cl ock. similarly, a synchroni zed reset is performed after a match with the cmdn register and after an overflow. 3. the count clock must not be changed during a ti mer operation. if it is to be overwritten, it should be overwritten after the tmdcen bit is cleared (0). 4. up to 4 clocks are required after a value is set in the tmdcen bit until the set value is transferred to internal units. when a c ount operation begins, the count cycle from 0000h to 0001h differs from subsequent cycles. 5. after a compare match is generated, the timer is cleared at the next count clock. therefore, if the division ratio is large, the timer value may not be zero even if the timer value is read immediately after a match interrupt is generated.
chapter 10 timer/counter function (real-time pulse unit) 282 user's manual u14980ej2v1ud (2) compare registers d0 to d3 (cmd0 to cmd3) cmdn and the tmdn register count value are comp ared, and an interrupt request signal (intcmdn) is generated when a match occurs. tmdn is cleared, synch ronized with this match. if the tmdcaen bit of the tmcdn register is set to 0, a reset is performed asynch ronously, and the registers are initialized (n = 0 to 3). the cmdn registers are configured with a master/slave configuration. when a write operation to a cmdn register is performed, data is first written to the master register and then the master register data is transferred to the slave register. in a compare operation, the slave register value is compared with the count value of the tmdn register. when a read operation to a cmdn register is performed, data in the master side is read out. cmdn can be read or written in 16-bit units. cautions 1. a write operation to a cmdn register re quires 4 clocks until the value that was set in the cmdn register is transferred to internal units. when writing continuously to the cmdn register, be sure to reserve a time interval of at least 4 clocks. 2. the cmdn register can be overwritten on ly once in a single tmdn register cycle (from 0000h until an intcmdn interrupt is generated due to a matc h of the tmdn register and cmdn register). if this cannot be secured by the application, make sure that the cmdn register is not overwritte n during timer operation. 3. note that a match signal will be generated after an overfl ow if a value less than the counter value is written in the cmdn regist er during tmdn register operation (figure 10- 13). cmd1 fffff552h 0000h cmd2 fffff562h 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cmd0 fffff542h 0000h address after reset 0 cmd3 fffff572h 0000h
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 283 figure 10-13. example of ti ming during tmdn operation (a) when tmdn < cmdn tmdn tmdcaen tmdcen cmdn intcmdn mn n n remark m = tmdn value when overwritten n = cmdn value when overwritten m < n (b) when tmdn > cmdn tmdn tmdcaen tmdcen cmdn intcmdn m ffffh n n n remark m = tmdn value when overwritten n = cmdn value when overwritten m > n
chapter 10 timer/counter function (real-time pulse unit) 284 user's manual u14980ej2v1ud 10.2.5 timer d control registers (1) timer mode control register s d0 to d3 (tmcd0 to tmcd3) the tmcdn registers control the operation of timer dn (n = 0 to 3). these registers can be read or wr itten in 8-bit or 1-bit units. caution the tmdcaen and other bits cannot be set at the same time. the other bits and the registers of the other tmdn unit should always be set after the tmdcaen bit has been set. (1/2) 7 6 5 4 3 2 <1> <0> address after reset tmcd0 0 cs02 cs01 cs00 0 0 tmdce0 tmdcae0 fffff544h 00h tmcd1 0 cs12 cs11 cs10 0 0 tmdce1 tmdcae1 fffff554h 00h tmcd2 0 cs22 cs21 cs20 0 0 tmdce2 tmdcae2 fffff564h 00h tmcd3 0 cs32 cs31 cs30 0 0 tmdce3 tmdcae3 fffff574h 00h bit position bit name function count enable select selects the tmdn internal count clock cycle (n = 0 to 3). csn2 csn1 csn0 count cycle 0 0 0 f xx /4 0 0 1 f xx /8 0 1 0 f xx /16 0 1 1 f xx /32 1 0 0 f xx /64 1 0 1 f xx /128 1 1 0 f xx /256 1 1 1 f xx /512 6 to 4 csn2 to csn0 (n = 0 to 3) caution the csn2 to csn0 bits must not be changed during timer operation. if they are to be changed, they must be changed after setting the tmdcen bit to 0. if these bits are overwritten during timer operation, operation cannot be guaranteed. remark f xx : internal system clock 1 tmdcen (n = 0 to 3) count enable controls the operation of tmdn (n = 0 to 3). 0: count disabled (stops at 0000h and does not operate) 1: counting operation is performed caution tmdcen bit is not cleared even if a match is detected by the compare operation. to the stop count operation, clear the tmdcen bit.
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 285 (2/2) bit position bit name function 0 tmdcaen (n = 0 to 3) clock action enable controls the internal count clock (n = 0 to 3). 0: the entire tmdn unit is reset asyn chronously. the supply of input clocks to the tmdn unit stops. 1: input clocks are supplied to the tmdn unit cautions 1. when the tmdcaen bit is set to 0, the tmdn unit can be asynchronously reset. 2. when tmdcaen = 0, the tmdn unit is in a reset state. therefore, to operate tmdn, the tmdcaen bit must be set to 1. 3. if the tmdcaen bit is cleared to 0, all the registers of the tmdn unit are initialized. if tmdcaen is set to 1 again, be sure to subsequently set all the registers of the tmdn unit again.
chapter 10 timer/counter function (real-time pulse unit) 286 user's manual u14980ej2v1ud 10.2.6 timer d operation (1) compare operation tmdn can be used for a compare operation in which the va lue that was set in a compare register (cmdn) is compared with the tmdn count value (n = 0 to 3). if a match is detected by the compare operation, an in terrupt (intcmdn) is generated. the generation of the interrupt causes tmdn to be cleared (0) at the next count timing. this function enables timer d to be used as an interval timer. cmdn can also be set to 0. in this case, when an overflow occurs and tmdn becomes 0, a match is detected and intcmdn is generated. although the tmdn value is cleared (0) at the next count timing, intcmdn is not generated by this match. figure 10-14. tmd0 compar e operation example (1/2) (a) when cmd0 is set to n (non-zero) 1 tmd0 count clock 0 n cmd0 n tmd0 clear match detected (intcmd0) count up clear remark interval time = (n + 1) count clock cycle n = 1 to 65,536 (ffffh)
chapter 10 timer/counter function (real-time pulse unit) user's manual u14980ej2v1ud 287 figure 10-14. tmd0 compar e operation example (2/2) (b) when cmd0 is set to 0 1 0 0 0 ffffh overflow tmd0 count clock cmd0 tmd0 clear match detected (intcmd0) count up clear remark interval time = (ffffh + 2) count clock cycle
chapter 10 timer/counter function (real-time pulse unit) 288 user's manual u14980ej2v1ud 10.2.7 application examples (timer d) (1) interval timer this section explains an example in which timer d is used as an interval timer with 16-bit precision. interrupt requests (intcmdn) are out put at equal intervals (refer to figure 10-14 tmd0 compare operation example ). the setup procedure is shown below (n = 0 to 3). <1> set (1) the tmdcaen bit. <2> set each register. ? select the count clock using the csn0 to csn2 bits of the tmcdn registers. ? set the compare value in the cmdn register. <3> start counting by setting (1) the tmdcen bit. <4> if the tmdn register and cmdn register va lues match, an intcmdn interrupt is generated. <5> intcmdn interrupts are generated thereafter at equal intervals. remark n = 0 to 3 10.2.8 precautions (timer d) various precautions concerning timer d are shown below. (1) to operate tmdn, first set (1) the tmdcaen bit. (2) up to 4 clocks are required after a value is set in the tmdcen bit until the set value is transferred to internal units. when a count operation begins, the count cycle from 0000h to 0001h differs from subsequent cycles. (3) to initialize the tmdn register st atus and start counting again, clear (0) the tmdcen bit and then set (1) the tmdcen bit after an interval of 4 clocks has elapsed. (4) up to 4 clocks are required until the value that was se t in the cmdn register is transferred to internal units. when writing continuously to the cmdn register, be sure to secure a time interval of at least 4 clocks. (5) the cmdn register can be overwr itten only once during a timer/coun ter operation (from 0000h until an intcmdn interrupt is generated due to a match of the tmdn register and cmdn regist er). if this cannot be secured, make sure that the cmdn register is not overwritten during a ti mer/counter operation. (6) the count clock must not be changed during a timer oper ation. if it is to be overwritten, it should be overwritten after the tmdcen bit is cleared (0). if t he count clock is overwritt en during a timer operation, operation cannot be guaranteed. (7) a match signal will be generated after an overflow if a value less than the counter value is written in the cmdn register during tmdn register operation. remark n = 0 to 3
user's manual u14980ej2v1ud 289 chapter 11 serial interface function 11.1 features the serial interface function provides two types of serial interfaces equipped with four transmit/receive channels of which two channels can be used simultaneously. the following two interface formats are available. (1) asynchronous serial interface (uart0, uart1): 2 channels (2) clocked serial interface (csi0, csi1): 2 channels uart0 and uart1, which use the method of transmitting/receiving one byte of serial data following a start bit, enable full-duplex communication to be performed. csi0 and csi1 transfer data according to three types of si gnals (3-wire serial i/o). these signals are the serial clock (sck0, sck1), serial input (si0, si 1), and serial output (so0, so1) signals. 11.1.1 switching between uart and csi modes in the v850e/ma2, since uart0 and csi0 pin and the ua rt1 and csi1 pin are alternate function pins, they cannot be used at the same time. the pmc4 and pfc4 registers must be set in advance (refer to 13.3.4 port 4 ). if the mode is switched during a transmit or receive operat ion in uartn or csin, operat ion cannot be guaranteed.
chapter 11 serial interface function user's manual u14980ej2v1ud 290 11.2 asynchronous serial interfaces 0, 1 (uart0, uart1) 11.2.1 features ? transfer rate: 300 bps to 1,250 kbps (using a dedicated baud rate generator and an internal system clock of 40 mhz) ? full-duplex communications on-chip receive buffer (rxbn) on-chip transmit buffer (txbn) ? two-pin configuration txdn: transmit data output pin rxdn: receive data input pin ? reception error detection function ? parity error ? framing error ? overrun error ? interrupt sources: 3 types ? reception error interrupt (intsern): interrupt is generated according to the logical or of the three types of reception errors ? reception completion interrupt (intsrn): interrupt is generated when receive data is transferred from the shift register to the receive buffer after serial transfer is completed during a reception enabled state ? transmission completion interrupt (intstn): interr upt is generated when the serial transmission of transmit data (8 or 7 bits) from the shift register is completed ? the character length of transmit/receive data is specified according to the asim0 and asim1 registers ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? on-chip dedicated baud rate generator remark n = 0, 1
chapter 11 serial interface function user's manual u14980ej2v1ud 291 11.2.2 configuration uartn is controlled by the asynchronous serial interface mode register (asimn), asynchronous serial interface status register (asisn), and asynchronous serial interface transmission status register (asifn) (n = 0, 1). receive data is maintained in the receive buffer (rxbn), and tr ansmit data is written to the transmit buffer (txbn). figure 11-1 shows the configuration of the asynchronous serial interface. (1) asynchronous serial interface mode registers 0, 1 (asim0, asim1) the asimn register is an 8-bit register for specifying the operation of the asynch ronous serial interface. (2) asynchronous serial interface stat us registers 0, 1 (asis0, asis1) the asisn register consists of a set of flags that indicate the error contents when a reception error occurs. the various reception error flags are set (1) when a re ception error occurs and are reset (0) when the asisn register is read. (3) asynchronous serial interface transmissi on status registers 0, 1 (asif0, asif1) the asifn register is an 8-bit regist er that indicates the status when a transmit operation is performed. this register consists of a transmit buffer data flag, which indicates the hold status of txbn data, and the transmit shift register data flag, which indi cates whether transmission is in progress. (4) reception control parity check the receive operation is controlled according to the c ontents set in the asimn register. a check for parity errors is also performed during a re ceive operation, and if an error is detected, a value corresponding to the error contents is set in the asisn register. (5) receive shift register this is a shift register that converts the serial data t hat was input to the rxdn pin to parallel data. one byte of data is received, and if a stop bi t is detected, the receive data is transferred to the receive buffer. this register cannot be directly manipulated. (6) receive buffer (rxbn) rxbn is an 8-bit buffer register for holding receive data. when 7 characters are received, 0 is stored in the msb. during a reception enabled state, re ceive data is transferred from the rece ive shift register to the receive buffer, synchronized with the end of t he shift-in processing of one frame. also, the reception completion interrupt request (intsr n) is generated by the transfe r of data to the receive buffer. (7) transmit shift register this is a shift register that converts the parallel data that was transferred from the transmit buffer to serial data. when one byte of data is transferred from the transmit buf fer, the shift register data is output from the txdn pin. this register cannot be directly manipulated.
chapter 11 serial interface function user's manual u14980ej2v1ud 292 (8) transmit buffer (txbn) txbn is an 8-bit buffer for transmit data. a transmit ope ration is started by writing transmit data to txbn. the transmission completion interrupt request (intstn) is generated synchronized with the completion of transmission of one frame. (9) addition of transmission control parity a transmit operation is controlled by adding a start bit, par ity bit, or stop bit to the dat a that is written to the txbn register, according to the contents that were set in the asimn register. figure 11-1. asynchronous se rial interface block diagram parity framing overrun internal bus asynchronous serial interface mode register n (asimn) receive buffer (rxbn) receive shift register reception control parity check transmit buffer (txbn) transmit shift register addition of transmission control parity brgn intsern intsrn intstn rxdn txdn remark n = 0, 1
chapter 11 serial interface function user's manual u14980ej2v1ud 293 11.2.3 control registers (1) asynchronous serial interface mode registers 0, 1 (asim0, asim1) these are 8-bit registers for controlling t he transfer operations of uart0 and uart1. these registers can be read or wr itten in 8-bit or 1-bit units. caution to use uartn, be sure to set the externa l pins related to the uartn function in control mode and set clock select register n (cksrn) and baud rate generato r control register n (brgcn). then set the uartcaen bit to 1 before setting the other bits. (1/3) <7> <6> <5> 4 3 2 1 0 address after reset asim0 uartcae0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 fffffa00h 01h asim1 uartcae1 txe1 rxe1 ps11 ps10 cl1 sl1 isrm1 fffffa10h 01h bit position bit name function 7 uartcaen (n = 0, 1) clock enable controls the operation clock (n = 0, 1). 0: stop supply of clocks to uartn unit 1: supplies clocks to uartn unit cautions 1. when the uartcaen bit is set to 0, the uartn unit can be asynchronously reset. 2. when uartcaen = 0, the uartn unit is in a reset state. therefore, to operate uartn, the uartcaen bit must be set to 1. 3. when the uartcaen bit is changed from 1 to 0, all registers of the uartn unit are initialized. when the uartcaen is set to 1 again, the uartn unit registers must be set again. the txdn pin output is always high level in transmit disable state, irrespective of the setting of uartcaen bit. 6 txen (n = 0, 1) transmit enable specifies whether transmis sion is enabled or disabled. 0: transmission is disabled 1: transmission is enabled cautions 1. on startup, set uartcaen to 1 and then set txen to 1. to stop transmission, clear txen to 0 and then uartcaen to 0. 2. when the transmission unit status is to be initialized, the transmission status may not be able to be initialized unless the txen bit is set (1) again after an interval of two cycles of the basic clock has elapsed since the txen bit was cleared (0) (for the basic clock, refer to 11.2.6 (1) (a) basic clock (clock)).
chapter 11 serial interface function user's manual u14980ej2v1ud 294 (2/3) bit position bit name function 5 rxen (n = 0, 1) receive enable specifies whether reception is enabled or disabled. 0: reception is disabled 1: reception is enabled cautions 1. on startup, set uartcaen to 1 and then set rxen to 1. to stop transmission, clear rxen to 0 and then uartcaen to 0. 2. when the reception unit status is to be initialized, the reception status may not be able to be initialized unless the rxen bit is set (1) again after an interval of two cycles of the basic clock has elapsed since the rxen bit was cleared (0) (for the basic clock, refer to 11.2.6 (1) (a) basic clock (clock)) . parity select controls the parity bit. psn1 psn0 transmit operation receive operation 0 0 do not output a parity bit receive with no parity 0 1 output 0 parity receive as 0 parity 1 0 output odd parity judge as odd parity 1 1 output even parity judge as even parity cautions 1. to overwrite the psn1 and psn0 bits, first clear (0) the txen and rxen bits. 2. if ?0 parity? is selected for reception, no parity judgement is made. therefore, no error interrupt is generated because the pen bit of the asisn register is not set. 4, 3 psn1, psn0 (n = 0, 1) ? even parity if the transmit data contains an odd number of bits with the value ?1?, the parity bit is set (1). if it contains an even number of bits with the value ?1?, the parity bit is cleared (0). this controls the num ber of bits with the value ?1? contained in the transmit data and the parity bit so that it is an even number. during reception, the number of bits wi th the value ?1? contained in the receive data and the parity bit is counted, and if the number is odd, a parity error is generated. ? odd parity in contrast to even parity, odd parity c ontrols the number of bits with the value ?1? contained in the transmit data and the parity bit so that it is an odd number. during reception, the number of bits wi th the value ?1? contained in the receive data and the parity bit is counted, and if the number is even, a parity error is generated. ? 0 parity during transmission, the parity bit is cleared (0) regardless of the transmit data. during reception, no parity error is gener ated because no parity bit is checked. ? no parity no parity bit is added to transmit data. during reception, the receive data is considered to have no parity bit. no parity error is generated because there is no parity bit.
chapter 11 serial interface function user's manual u14980ej2v1ud 295 (3/3) bit position bit name function 2 cln (n = 0, 1) character length specifies the character length of the transmit/receive data. 0: 7 bits 1: 8 bits caution to overwrite the cln bit, first clear (0) the txen and rxen bits. 1 sln (n = 0, 1) stop bit length specifies the stop bit length of the transmit data. 0: 1 bit 1: 2 bits cautions 1. when overwriting the sln bit, first clear (0) the txen bit. 2. since reception always operates by using a 1-bit stop bit, the sln bit setting does not affect receive operations. 0 isrmn (n = 0, 1) interrupt serial receive mode specifies whether the generation of recept ion completion interrupt requests when an error occurs is enabled or disabled. 0: a reception error interrupt request (intsern) is generated when an error occurs. in this case, no reception co mpletion interrupt request (intsrn) is generated. 1: a reception completion interrupt request (intsrn) is generated when an error occurs. in this case, no reception error interrupt request (intsern) is generated. caution when overwriting the isrmn bit, first clear (0) the rxen bit. remark when reception is disabled, the receive shift regi ster does not detect a start bit. no shift-in processing or transfer processing to the receive buffe r is performed, and the contents of the receive buffer are retained. when reception is enabled, the receive shift operat ion starts, synchronized with the detection of the start bit, and when the reception of one frame is comple ted, the contents of the receive shift register are transferred to the receive buffer. a reception completion interrupt (intsrn) is also generated, synchronized with the transfer to the receive buffer.
chapter 11 serial interface function user's manual u14980ej2v1ud 296 (2) asynchronous serial interface stat us registers 0, 1 (asis0, asis1) these registers, which consist of 3-bit error flags ( pen, fen, and oven), indicate the error status when uartn reception is completed (n = 0, 1). the status flag, which indicates a reception error, alwa ys indicates the status of t he error that occurred most recently. that is, if the same error occurred several times before the receive data was read, this flag would hold only the status of the error that occurred last. the asisn register is cleared to 00h by a read operat ion. when a reception error occurs, the receive buffer (rxbn) should be read after the asisn register is read. these registers are read-only in 8-bit units. caution when the uartcaen bit or r xen bit of the asimn register is set to 0, or when the asisn register is read, the pen, fen, and oven bi ts of the asisn register are cleared (0). 7 6 5 4 3 2 1 0 address after reset asis0 0 0 0 0 0 pe0 fe0 ove0 fffffa03h 00h asis1 0 0 0 0 0 pe1 fe1 ove1 fffffa13h 00h bit position bit name function 2 pen (n = 0, 1) parity error this is a status flag that indicates a parity error. 0: when the uartcaen and rxen bits of the asimn register are cleared to 0 or when the asisn register is read 1: when reception was completed, the transmit data parity did not match the parity bit caution the operation of the pen bit differs according to the settings of the psn1 and psn0 bits of the asimn register. 1 fen (n = 0, 1) framing error this is a status flag that indicates a framing error. 0: when the uartcaen and rxen bits of the asimn register are cleared to 0 or when the asisn register is read 1: when reception was completed, no stop bit was detected caution for receive data stop bits, only the first bit is checked regardless of the stop bit length. 0 oven (n = 0, 1) overrun error this is a status flag that indicates an overrun error. 0: when the uartcaen and rxen bits of the asimn register are cleared to 0 or when the asisn register is read 1: uartn completed the next receive operation before reading the rxbn receive data. caution when an overrun error occurs, the next receive data value is not written to the rxbn register and the data is discarded.
chapter 11 serial interface function user's manual u14980ej2v1ud 297 (3) asynchronous serial interface transmissi on status registers 0, 1 (asif0, asif1) these registers, which consist of 2-bit status flags, indicate the status during transmission. by writing the next data to the txbn register after data is transferred from the txbn register to the txsn register, transmit operations can be performed contin uously without suspension even during an interrupt interval. when transmission is performed continuously, data should be written after referencing the txbfn bit of the asifn register to prevent writ ing to the txbn register by mistake. these registers are read-only in 8-bit or 1-bit units. remark n = 0, 1 7 6 5 4 3 2 <1> <0> address after reset asif0 0 0 0 0 0 0 txbf0 txsf0 fffffa05h 00h asif1 0 0 0 0 0 0 txbf1 txsf1 fffffa15h 00h bit position bit name function 1 txbfn (n = 0, 1) transmit buffer flag this is a transmit buffer data flag. 0: no data to be transferred next exists in the txbn register (when the uartcaen or txen bit of the asimn register is cleared to 0 or when data has been transferred to the transmit shift register) 1: data to be transferred next exists in the txbn register (when data has been written to the txbn register). caution to successively transmit data, make sure that this flag is 0, and then write data to the txbn register. if data is written to the txbn register while this flag is 1, the transmit data cannot be guaranteed. 0 txsfn (n = 0, 1) transmit shift flag this is a transmit shift register data fl ag. it indicates the transmission status of uartn. 0: initial status or waiting for transmission (when the uartcaen or txen bit of the asimn register is cleared to 0 or if no next data is transferred from the txbn register after completion of transfer). 1: under transmission (if data is tran sferred from the txbn register) caution before initializing the transmit unit, make sure that this flag is 0 after occurrence of the transmission completion interrupt. if initialization is executed while this flag is 1, the transmit data is not guaranteed.
chapter 11 serial interface function user's manual u14980ej2v1ud 298 (4) receive buffer registers 0, 1 (rxb0, rxb1) these are 8-bit buffer registers for st oring parallel data that had been conver ted by the receive shift register. when reception is enabled (rxen = 1 in the asimn register ), receive data is transferred from the receive shift register to the receive buffer, synchronized with the comp letion of the shift-in processing of one frame. also, a reception completion interrupt request (intsrn) is generated by the transfer to the receive buffer. for information about the timing for generatin g these interrupt requests, refer to 11.2.5 (4) receive operation . if reception is disabled (rxen = 0 in the asimn registe r), the contents of the receive buffer are retained, and no processing is performed for transferring data to the receive buffer even when the shift-in processing of one frame is completed. also, no reception completion interrupt is generated. when 7 bits is specified for the data length, bits 6 to 0 of the rxbn register are transferred for the receive data and the msb (bit 7) is always 0. however, if an overrun error occurs, the receive data at that time is not transferred to the rxbn register. except when a reset is input, the rxbn register becomes ffh even when uartcaen = 0 in the asimn register. these registers are read-only in 8-bit units. remark n = 0, 1 7 6 5 4 3 2 1 0 address after reset rxb0 rxb07 rxb06 rxb05 rxb04 rxb03 rxb02 rxb01 rxb00 fffffa02h ffh rxb1 rxb17 rxb16 rxb15 rxb14 rxb13 rxb12 rxb11 rxb10 fffffa12h ffh bit position bit name function 7 to 0 rxbn7 to rxbn0 (n = 0, 1) receive buffer stores receive data. 0 can be read for rxbn7 when 7-bit or character data is received.
chapter 11 serial interface function user's manual u14980ej2v1ud 299 (5) transmit buffer registers 0, 1 (txb0, txb1) these are 8-bit buffer registers for setting transmit data. when transmission is enabled (txen = 1 in the asimn regi ster), the transmit operat ion is started by writing data to txbn. when transmission is disabled (txen = 0 in the asimn regist er), even if data is written to txbn, the value is ignored. the txbn data is transferred to the transmit shift regi ster, and a transmission completion interrupt request (intstn) is generated, synchronized with the completion of the transmission of one frame from the transmit shift register. for information about the timing for generating these interrupt requests, refer to 11.2.5 (2) transmit operation . when txbfn = 1 in the asifn register, wr iting must not be performed to txbn. these registers can be read or written in 8-bit units. remark n = 0, 1 7 6 5 4 3 2 1 0 address after reset txb0 txb07 txb06 txb05 txb04 txb 03 txb02 txb01 txb00 fffffa04h ffh txb1 txb17 txb16 txb15 txb14 txb 13 txb12 txb11 txb10 fffffa14h ffh bit position bit name function 7 to 0 txbn7 to txbn0 (n = 0, 1) transmit buffer writes transmit data.
chapter 11 serial interface function user's manual u14980ej2v1ud 300 11.2.4 interrupt requests the following three types of interrupt reques ts are generated from uartn (n = 0, 1). ? reception error interrupt (intsern) ? reception completion interrupt (intsrn) ? transmission completion interrupt (intstn) the default priorities among these three types of interrupt requests is, from hi gh to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt. table 11-1. generated inte rrupts and default priorities interrupt priority reception error 1 reception completion 2 transmission completion 3 (1) reception error interrupt (intsern) when reception is enabled, a recepti on error interrupt is generated accordi ng to the logical or of the three types of reception errors explained for the asisn regist er. whether a reception error interrupt (intsern) or a reception completion interrupt (intsrn) is generated when an error occurs can be specified according to the isrmn bit of the asimn register. when reception is disabled, no rec eption error interrupt is generated. (2) reception completion interrupt (intsrn) when reception is enabled, a reception completion in terrupt is generated when dat a is shifted in to the receive shift register and transferred to the receive buffer. a reception completion interrupt request can be generated in place of a reception error interrupt according to the isrmn bit of the asimn register ev en when a reception error has occurred. when reception is disabled, no reception completion interrupt is generated. (3) transmission completion interrupt (intstn) a transmission completion interrupt is generated when one frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmit shift register.
chapter 11 serial interface function user's manual u14980ej2v1ud 301 11.2.5 operation (1) data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consis ts of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 11-2. the character bit length within one data frame, the ty pe of parity, and the st op bit length are specified according to the asynchronous serial inte rface mode register n (asimn) (n = 0, 1). also, data is transferred with the least significant bit (lsb) first. figure 11-2. asynchronous serial interface transmit/receive data format 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit 1 bit ? character bits 7 bits or 8 bits ? parity bit even parity, odd parity, 0 parity, or no parity ? stop bits 1 bit or 2 bits
chapter 11 serial interface function user's manual u14980ej2v1ud 302 (2) transmit operation when uartcaen is set to 1 in the asimn regist er, a high level is output to the txdn pin. then, when txen is set to 1 in the asimn register, transmission is enabled, and the transmit operation is started by writing transmit data to transmi t buffer register n (txbn) (n = 0, 1). (a) transmission enabled state this state is set by the txen bit in the asimn register (n = 0, 1). ? txen = 1: transmission enabled state ? txen = 0: transmission disabled state however, when the transmission enabled state is se t, to use uart0 and uart1, which share pins with clocked serial interfaces 0 and 1 (csi0 and csi1), the csicaen bit of clocked serial interface mode registers 0 and 1 (csim0 and csim1) should be set to 0. since uartn does not have a cts (transmission enab led signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (b) starting a transmit operation in transmission enabled state, a transmit operation is started by writing transmit data to transmit buffer register n (txbn). when a transmit operation is started, the data in tx bn is transferred to transmit shift register n (txsn). then, the txsn register outputs data to the txdn pin sequentially beginning with the lsb (the transmit data is transferred sequentially starting with the start bit). the start bit, parity bit, and stop bits are added automatically (n = 0, 1). (c) transmission interrupt request when the transmit shift register (txsn) becomes em pty, a transmission completion interrupt request (intstn) is generated. the timi ng for generating the intstn interrupt differs according to the specification of the stop bit length. the intstn interrupt is generated at the same time t hat the last stop bit is output (n = 0, 1). if the data to be transmitted next has not been written to the txbn regi ster, the transmit operation is suspended. caution normally, when transmit shift register n (txsn) becomes empty, a transmission completion interrupt (intstn) is generate d. however, no transmission completion interrupt (intstn) is generate d if transmit shift register n (txsn) becomes empty due to the input of reset.
chapter 11 serial interface function user's manual u14980ej2v1ud 303 figure 11-3. asynchronous serial interf ace transmission comple tion interrupt timing start stop d0 d1 d2 d6 d7 parity parity txdn (output) intstn (output) start d0 d1 d2 d6 d7 txdn (output) intstn interrupt stop (a) stop bit length: 1 (b) stop bit length: 2 remark n = 0, 1
chapter 11 serial interface function user's manual u14980ej2v1ud 304 (3) continuous transmission operation uartn can write the next data to the txbn register at the time that the txsn register starts the shift operation. this enables an efficient transmission rate to be realized by continuously transmitting data even during interrupt servicing after the transmission of one dat a frame (n = 0, 1). by reading the txsfn bit of the asifn register after the transmission completion interrupt has occurred, data can be efficiently written to the txbn register two times (2 bytes) without having to wait for the transmission time of 1 data frame. when continuous transmission is performed, data should be written after referencing the asifn register to confirm the transmission status and whether or not data can be written to the txbn register (n = 0, 1). txbfn enables/disables writi ng to the txbn register 0 enables writing. 1 disables writing. caution to successively transmit data, make sure that the txbfn bit is 0 after the first transmit data (first byte) has been written to the txbn regi ster, before writing the next transmit data (second byte) to the txbn register . if data is written to the txbn register while the txbfn bit is 1, the transmit data is not guaranteed. while successive transmission is under execution, whet her data has been written to the txbn register can be checked by checking the txsfn bit after occurr ence of the transmission completion interrupt. txsfn transmission status 0 transmission has been completed. however, note caution of the txbfn bit. transmit data can be written two times (2 bytes). 1 transmission is under execution. transmit data can be written once (1 byte). cautions 1. before initiali zing the transmit unit after comple tion of successive transmission, make sure that the txsfn bit is 0 after the transmission completion interrupt has occurred. if initialization is executed while the txsfn bit is 1, the transmit data cannot be guaranteed. 2. while data is being successively transmi tted, an overrun error may occur because the next transmission may be completed before the intstn interrupt servicing is executed after transmission of 1 data frame. the ove rrun error can be detected by incorporating a program that can count the number of transm it data and by refere ncing the txsfn bit.
chapter 11 serial interface function user's manual u14980ej2v1ud 305 figure 11-4. continuous transmission processing flow interrupt occurs. no no no no yes yes transfer executed necessary number of times? write transmit data to txbn register. txsfn = 1 when asifn register is read? txsfn = 0 when asifn register is read? txbfn = 0 when asifn register is read? end of transmission processing wait for interrupt. yes yes set registers. write transmit data to txbn register. remark n = 0, 1
chapter 11 serial interface function user's manual u14980ej2v1ud 306 (a) starting procedure the procedure for starting continuous transmission is shown below. figure 11-5. continuous tr ansmission starting procedure txdn (output) data (1) data (2) <5> <1> <2> <4> intstn (output) txbn register ffh ffh data (1) data (2) data (3) data (1) data (2) data (3) <3> asifn register (txbfn and txsfn bits) 00 10 11 01 01 11 01 11 txsn register start bit start bit stop bit stop bit note note because this period is a period of transition from ? 10? to ?01?, ?11? or ?00? may be read if the txbfn and txsfn bits of the asifn regist er are simultaneously read. theref ore, use only the txbfn bit to judge whether data can be wri tten to the txbn register. remark n = 0, 1 asifn register transmission starting procedure internal operation txbfn txsfn ? set transmission mode <1> start transmission unit 0 0 ? write data (1) 1 0 <2> generate start bit start data (1) transmission ? read asifn register (confirm that txbfn bit = 0) 1 0 0 0 1/0 note 1/0 note 1 1 ? write data (2) <> 1 1 <3> generate intstn interrupt ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (3) <4> generate start bit start data (2) transmission <> 1 1 <5> generate intstn interrupt ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (4) 1 1 note transition period
chapter 11 serial interface function user's manual u14980ej2v1ud 307 (b) ending procedure the procedure for ending continuous transmission is shown below. figure 11-6. continuous transmission ending procedure txdn (output) data (m ? 1) data (m) <11> <7> <6> <8> <10> intstn (output) txbn register data (m ? 1) data (m ? 1) data (m) ffh data (m) <9> asifn register (txbfn and txsfn bits) uartcaen bit or txen bit 11 01 11 01 00 txsn register start bit stop bit stop bit start bit remark n = 0,1 asifn register transmission ending procedure internal operation txbfn txsfn <6> transmission of data (m ? 2) is in progress 1 1 <7> generate intst interrupt ? read asifn register (confirm that the txbfn bit = 0) 0 0 1 1 ? write data (n) <8> generate start bit start data (m ? 1) transmission <> 1 1 <9> generate intstn interrupt ? read asifn register (confirm that the txsfn bit = 1) there is no write data <10> generate start bit start data (m) transmission <> 0 0 1 1 <11> generate intstn interrupt ? read asifn register (confirm that the txsfn bit = 0) ? clear (0) the uartcaen bit or txen bit initialize internal circuits 0 0 0 0
chapter 11 serial interface function user's manual u14980ej2v1ud 308 (4) receive operation an awaiting reception state is set by setting uartcaen to 1 in the asimn register and then setting rxen to 1 in the asimn register. rxdn pin sampling begins and a start bit is detected. when the start bit is detected, the receive operation begins, and data is stored sequentially in the receive shift register according to the baud rate that was set. a reception completion interrupt (intsrn) is generated each time the reception of one frame of data is completed. normally, the receive da ta is transferred from the receive buffer (rxbn) to memory by this interrupt servicing (n = 0, 1). (a) reception enabled state the receive operation is set to reception enabled stat e by setting the rxen bit in the asimn register to 1 (n = 0, 1). ? rxen = 1: reception enabled state ? rxen = 0: reception disabled state however, when the reception enabled state is se t, to use uart0 and uart1, which share pins with clocked serial interfaces 0 and 1 (csi0 and csi1), the operation of csin must be disabled by setting the csicaen bit of clocked serial interface mode regist ers 0 and 1 (csim0 and csim1) to 0 (n = 0, 1). in reception disabled state, the rece ption hardware stands by in the initial state. at this time, the contents of the receive buffer are retained, and no reception co mpletion interrupt or reception error interrupt is generated. (b) starting a receive operation a receive operation is started by the detection of a start bit. the rxdn pin is sampled according to the serial cl ock from the baud rate generator (brgn) (n = 0, 1). (c) reception completion interrupt when rxen = 1 in the asimn register and the reception of one frame of data is completed (the stop bit is detected), a reception completion inte rrupt (intsrn) is generated and t he receive data within the receive shift register is transferred to rxbn at the same time (n = 0, 1). also, if an overrun error occurs, the receive data at that time is not transferred to the receive buffer (rxbn), and either a reception completion interrupt (i ntsrn) or a reception error interrupt (intsern) is generated according to the isrmn bit setting in the asimn register. even if a parity error or framing error occurs during a receive operation, the receive operation continues until a stop bit is received, and after reception is completed, either a reception completion interrupt (intsrn) or a reception error inte rrupt (intsern) is generated (the rece ive data within the receive shift register is transferred to rxbn) according to the isrmn bit setting in the asimn register. if the rxen bit is reset (0) during a receive operation, the receive operation is immediately stopped. the contents of the receive buffer (rxbn) and of the asynchr onous serial interface status register (asisn) at this time do not change, and no reception completion interrupt (intsrn) or reception error interrupt (intsern) is generated. no reception completion interrupt is generated when rxen = 0 (reception is disabled).
chapter 11 serial interface function user's manual u14980ej2v1ud 309 figure 11-7. asynchronous serial interf ace reception completion interrupt timing start d0 d1 d2 d6 d7 rxdn (input) intsrn (output) rxbn register parity stop cautions 1. be sure to read the receive buffer (rxbn) when a reception error occurs. unless rxbn is read, an o verrun error occurs when the n ext data is received, causing the reception error status to continue. 2. data is always received with a stop bit length of 1 bit. a second stop bit is ignored. remark n = 0, 1 (5) reception error the three types of error that can occur during a receive operation are a parity error, framing error, or overrun error. the data reception result is that the various flags of the asisn register are set (1), and a reception error interrupt (intsern) or a reception completion in terrupt (intsrn) is generated at the same time. the isrmn bit of the asimn register specifies whether intsern or intsrn is generated. the type of error that occurred during reception c an be detected by reading th e contents of the asisn register during the intsern or intsrn interrupt servicing. the contents of the asisn r egister are reset (0) by reading the asisn register. table 11-2. reception error causes error flag reception error cause pen parity error the parity specificat ion during transmission did not match the parity of the reception data fen framing error no stop bit was detected oven overrun error the reception of the next data was completed before data was read from the receive buffer remark n = 0, 1
chapter 11 serial interface function user's manual u14980ej2v1ud 310 (a) separation of rece ption error interrupt a reception error interrupt can be separated from the intsrn interrupt and generated as an intsern interrupt by clearing the isrmn bit of t he asimn register (n = 0, 1) to 0. figure 11-8. when reception error interrupt is se parated from ints rn interrupt (isrmn bit = 0) (a) no error occurs during reception (b) an e rror occurs during reception intsrn (output) (reception completion interrupt) intsern (output) (reception error interrupt) intsrn (output) (reception completion interrupt) intsern (output) (reception error interrupt) remark n = 0, 1 figure 11-9. when reception error interrupt is in cluded in intsrn inte rrupt (isrmn bit = 1) (a) no error occurs during reception (b) an erro r occurs during reception intsrn (output) (reception completion interrupt) intsern (output) (reception error interrupt) intsrn (output) (reception completion interrupt) intsern (output) (reception error interrupt) remark n = 0, 1
chapter 11 serial interface function user's manual u14980ej2v1ud 311 (6) parity types and co rresponding operation a parity bit is used to detect a bit error in communication data. normally, the same type of parity bit is used at the transmission and reception sides. (a) even parity (i) during transmission the parity bit is controlled so t hat the number of bits with the value ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1? within the transmit data is even: 0 (ii) during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (b) odd parity (i) during transmission in contrast to even parity, the parity bit is contro lled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1? within the transmit data is even: 1 (ii) during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (d) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no parity bit. since there is no parity bit, no parity error is generated.
chapter 11 serial interface function user's manual u14980ej2v1ud 312 (7) receive data noise filter the rxdn signal is sampled at the rising edge of the prescaler output clock. if the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (refer to figure 11-11 ). refer to 11.2.6 (1) (a) basic clock (clock) regarding the basic clock. also, since the circuit is configured as shown in figur e 11-10, internal processing during a receive operation is delayed by up to 2 clocks accord ing to the external signal status. figure 11-10. noise filter circuit rxdn q clock in ld_en q in a internal signal b internal signal match detector remark n = 0, 1 figure 11-11. timing of rx dn signal judg ed as noise internal signal a clock rxdn (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match remark n = 0, 1
chapter 11 serial interface function user's manual u14980ej2v1ud 313 11.2.6 dedicated baud rate gene rators 0, 1 (brg0, brg1) a dedicated baud rate generator, which consists of a s ource clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception in uartn. the dedicated baud rate generator output can be selected as the serial clock for each channel. separate 8-bit counters exist fo r transmission and for reception. (1) baud rate genera tor configuration figure 11-12. baud rate generator configuration f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xx /2,048 clock (f xclk ) selector uartcaen 8-bit counter match detector baud rate brgcn: brgn7 to brgn0 1/2 uartcaen and txen (or rxen) cksrn: tpsn3 to tpsn0 f xx remarks 1. n = 0, 1 2. f xx : internal system clock (a) basic clock (clock) when uartcaen = 1 in the asimn register, the clock selected according to the tpsn3 to tpsn0 bits of the cksrn register is supplied to the transmission/rec eption unit. this clock is called the basic clock, and its frequency is referred to as f xclk . when uartcaen = 0, the clock signal is fixed at low level.
chapter 11 serial interface function user's manual u14980ej2v1ud 314 (2) serial clock generation a serial clock can be generated according to the setti ngs of the cksrn and brgcn registers (n = 0, 1). the input clock to the 8-bit counter is selected accord ing to the tpsn3 to tpsn0 bits of the cksrn register. the 8-bit counter divisor value can be selected acco rding to the brgn7 to brgn0 bits of the brgcn register. (a) clock select registers 0, 1 (cksr0, cksr1) the cksrn register is an 8-bit register for select ing the input block according to the tpsn3 to tpsn0 bits. the clock selected by the tpsn3 to tpsn0 bits becomes the basic clock of the transmission/ reception module. its frequency is referred to as f xclk . these registers can be read or written in 8-bit units. cautions 1. the maximum allowabl e frequency of the basic clock (f xclk ) is 20 mhz. therefore, when the system clock?s freque ncy is 40 mhz, bits tpsn3 to tpsn0 cannot be set to 0000b (n = 0, 1). if the system clock frequency is 40 mhz, set the tpsn3 to tpsn0 bits to a value other than 0000b and set the uartcaen bi t of the asimn register to 1. 2. if the tpsn3 to tpsn0 bits are to be overwritten, the uartcaen bit of the asimn register should be set to 0 first. 7 6 5 4 3 2 1 0 address after reset cksr0 0 0 0 0 tps03 tps02 tps01 tps00 fffffa06h 00h cksr1 0 0 0 0 tps13 tps12 tps11 tps10 fffffa16h 00h bit position bit name function specifies the basic clock tpsn3 tpsn2 tpsn1 tpsn0 basic clock (f xclk ) 0 0 0 0 f xx 0 0 0 1 f xx /2 0 0 1 0 f xx /4 0 0 1 1 f xx /8 0 1 0 0 f xx /16 0 1 0 1 f xx /32 0 1 1 0 f xx /64 0 1 1 1 f xx /128 1 0 0 0 f xx /256 1 0 0 1 f xx /512 1 0 1 0 f xx /1,024 1 0 1 1 f xx /2,048 1 1 arbitrary arbitrary setting prohibited 3 to 0 tpsn3 to tpsn0 (n = 0, 1) remark f xx : internal system clock
chapter 11 serial interface function user's manual u14980ej2v1ud 315 (b) baud rate generator control registers 0, 1 (brgc0, brgc1) the brgcn register is an 8-bit regist er that controls the baud rate (serial transfer speed) of uartn. these registers can be read or written in 8-bit units. caution if the brgn7 to brgn0 bits are to be overwritten, txen and rxen should be set to 0 in the asimn register first (n = 0, 1). 7 6 5 4 3 2 1 0 address after reset brgc0 mdl07 mdl06 mdl05 mdl04 mdl03 mdl02 mdl01 mdl00 fffffa07h ffh brgc1 mdl17 mdl16 mdl15 mdl14 mdl13 mdl12 mdl11 mdl10 fffffa17h ffh bit position bit name function specifies the 8-bit counter?s divisor value. brgn7 brgn6 brgn5 brgn4 brgn3 brgn2 brgn1 brgn0 divisor value (k) serial clock 0 0 0 0 0 ? setting prohibited 0 0 0 0 1 0 0 0 8 f xclk /8 0 0 0 0 1 0 0 1 9 f xclk /9 0 0 0 1 0 1 0 10 f xclk /10 1 1 1 1 1 0 1 0 250 f xclk /250 1 1 1 1 1 0 1 1 251 f xclk /251 1 1 1 1 1 1 0 0 252 f xclk /252 1 1 1 1 1 1 0 1 253 f xclk /253 1 1 1 1 1 1 1 0 254 f xclk /254 1 1 1 1 1 1 1 1 255 f xclk /255 7 to 0 brgn7 to brgn0 (n = 0, 1) remarks 1. f xclk : frequency of clock selected according to tpsn3 to tpsn0 bits of cksrn register. 2. k: value set according to brgn7 to brgn0 bits (k = 8, 9, 10, ..., 255) 3. : don?t care ? ? ? ? ? ? ? ? ? ?
chapter 11 serial interface function user's manual u14980ej2v1ud 316 (c) baud rate error the baud rate is the value obtained according to the following formula. [bps] k 2 f rate baud xclk = f xclk = frequency of basic clock selected according to tpsn3 to tpsn0 bits of cksrn register. k = value set according to brgn7 to brgn0 bits of brgcn register (k = 8, 9, 10, ..., 255) the baud rate error is obtained according to the following formula. [%] 100 1 rate) baud (normal rate baud desired error) with rate (baud rate baud actual (%) error ? = ? ? ? ? ? ? ? ? cautions 1. make sure that the baud rate erro r during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error duri ng reception is within th e allowable baud rate range during reception, which is described in paragraph (4). example: basic clock frequency = 20 mhz = 20,000,000 hz settings of brgn7 to brgn0 bits in brgcn register = 01000001b (k = 65) target baud rate = 153,600 bps baud rate = 20 m/(2 65) = 20,000,000/(2 65) = 153,846 [bps] error = (153,846/153,600 ? 1) 100 = 0.160 [%]
chapter 11 serial interface function user's manual u14980ej2v1ud 317 (3) baud rate setting example table 11-3. baud rate generator setting data f xx = 40 mhz f xx = 33 mhz f xx = 10 mhz baud rate (bps) f xclk k err f xclk k err f xclk k err 300 f xx /2 10 65 0.16 f xx /2 8 215 ?0.07 f xx /2 7 130 0.16 600 f xx /2 9 65 0.16 f xx /2 7 215 ?0.07 f xx /2 6 130 0.16 1,200 f xx /2 8 65 0.16 f xx /2 6 215 ?0.07 f xx /2 5 130 0.16 2,400 f xx /2 7 65 0.16 f xx /2 5 215 ?0.07 f xx /2 4 130 0.16 4,800 f xx /2 6 65 0.16 f xx /2 4 215 ?0.07 f xx /2 3 130 0.16 9,600 f xx /2 5 65 0.16 f xx /2 3 215 ?0.07 f xx /2 2 130 0.16 19,200 f xx /2 4 80 0.16 f xx /2 2 215 ?0.07 f xx /2 1 130 0.16 31,250 f xx /2 3 65 0 f xx /2 2 132 0 f xx /2 1 80 0 38,400 f xx /2 3 65 0.16 f xx /2 1 215 ?0.07 f xx /2 0 130 0.16 76,800 f xx /2 2 65 0.16 f xx /2 1 107 0.39 f xx /2 0 65 0.16 153,600 f xx /2 1 65 0.16 f xx /2 1 54 ?0.54 f xx /2 0 33 ?1.36 312,500 f xx /2 1 32 0 f xx /2 1 26 1.54 f xx /2 0 16 0 caution the maximum allowable fr equency of the basic clock (f xclk ) is 20 mhz. remarks f xx : internal system clock f xclk : basic clock k: settings of brgn7 to brgn0 bits in brgcn register (n = 0, 1) err: baud rate error [%]
chapter 11 serial interface function user's manual u14980ej2v1ud 318 (4) allowable baud rate range during reception the degree to which a discrepancy from the transmission destination?s baud rate is allowed during reception is shown below. caution the equations described be low should be used to set the baud rate error during reception so that it always is withi n the allowable error range. figure 11-13. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartn transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit remark n = 0, 1 as shown in figure 11-13, after the start bit is detect ed, the receive data latch timing is determined according to the counter that was set by the brgc n register. if all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. applying this to 11-bit reception is, theoretically, as follows. fl = (brate) ?1 brate: uartn baud rate (n = 0, 1) k: brgcn setting value (n = 0, 1) fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: fl k 2 2 k 21 fl k 2 2 k fl 11 flmin + = ? ? =
chapter 11 serial interface function user's manual u14980ej2v1ud 319 therefore, the transfer destination?s maximum baud rate that can be received is as follows. brate 2 21k k 22 (flmin/11) brmax 1 + = = ? similarly, the maximum allowable transfer rate can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 flmax 11 10 ? = + ? = 11 fl k 20 2 k 21 flmax ? = therefore, the transfer destination?s minimum baud rate that can be received is as follows. brate 2 21k k 20 (flmax/11) brmin 1 ? = = ? the allowable baud rate error of uartn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 11-4. maximum and mini mum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% ?3.61% 20 +4.26% ?4.31% 50 +4.56% ?4.58% 100 +4.66% ?4.67% 255 +4.72% ?4.73% remarks 1. the reception precision depends on the number of bits in one fr ame, the input clock frequency, and the division ratio (k). the higher the input clock frequency and the larger the division ratio (k), the higher the precision. 2. k: brgcn setting value (n = 0, 1)
chapter 11 serial interface function user's manual u14980ej2v1ud 320 (5) transfer rate durin g continuous transmission during continuous transmission, the tr ansfer rate from a stop bit to the ne xt start bit is extended two clocks longer than normal. however, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 11-14. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bit length by flstp, and the basic clock frequency by f xclk yields the following equation. flstp = fl + 2/f xclk therefore, the transfer rate during co ntinuous transmission is as follows. transfer rate = 11 fl + 2/f xclk 11.2.7 precautions the points to be noted when using uart n are described below (n = 0, 1). (1) when the supply of clocks to uart n is stopped (for example, idle or software stop mode), operation stops with each register retaining the value it had immediatel y before the supply of clocks was stopped. the txdn pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. however, operation is not gua ranteed after the supply of clocks is rest arted. therefore, after the supply of clocks is restarted, the circuits should be initialized by setting uartcaen = 0, rxen = 0, and txen = 0. (2) uartn has a two-buffer configuration, consisting of tr ansmit buffers (txbn) and transmit shift registers, and has status flags (txbfn and t xsfn bits of the asifn regi ster) that indicate the st atus of the respective buffers. if the txbfn and txsfn bits are read at the same time during successive transmission, these bits change from ?10? to ?01?. because this change timing is the data transition period from txbn to the transmit shift register, however, ?11? or ?00? may be read depending on the timing. to successively transmit data, therefore, read only the txbfn bit.
chapter 11 serial interface function user's manual u14980ej2v1ud 321 11.3 clocked serial interfaces 0, 1 (csi0, csi1) 11.3.1 features ? transfer rate: master mode: maximum 2.5 mbps (when internal system clock operates at 40 mhz) slave mode: maximum 4 mbps ? half-duplex communications ? master mode and slave mode can be selected ? transmission data length: 8 bits ? transfer data direction can be swit ched between msb first and lsb first ? eight clock signals can be selected (7 master clocks and 1 slave clock) ? 3-wire method son: serial data output sin: serial data input sckn: serial clock i/o ? interrupt sources: 1 type ? transmission/reception completion interrupt (intcsin) ? transmission/reception mode or recept ion-only mode can be specified ? on-chip transmit buffer (sotbn) remark n = 0, 1 11.3.2 configuration csin is controlled by the clocked serial interface mode regi ster (csimn) (n = 0, 1). transmit/receive data can be written to or read from the sion register. (1) clocked serial interface mode registers 0, 1 (csim0, csim1) the csimn register is an 8-bit register for specifying the operation of csin. (2) clocked serial interface clock select ion registers 0, 1 (csic0, csic1) the csicn register is an 8-bit register fo r controlling the transmit operation of csin. (3) serial i/o shift registers 0, 1 (sio0, sio1) the sion register is an 8-bit register for converting between serial data and parallel data. sion is used for both transmission and reception. data is shifted in (reception) or shifted out (transmissi on) beginning at either the msb side or the lsb side. actual transmit/receive operations are controll ed by reading or writing operations for sion. (4) clocked serial interface transmit bu ffer registers 0, 1 (sotb0, sotb1) the sotbn register is an 8-bit buffer register for storing transmit data. (5) selector the selector selects the serial clock to be used. (6) serial clock controller the serial clock controller controls the supply of serial clocks to the shift register. when an internal clock is used, it also controls the clocks that are output to the sckn pin.
chapter 11 serial interface function user's manual u14980ej2v1ud 322 (7) serial clock counter the serial clock counter counts serial clocks that are output or input during transmit and receive operations and checks that 8-bit data has been transmitted or received. (8) interrupt controller the interrupt controller controls whether or not an inte rrupt request is generated when the serial clock counter has counted eight serial clocks. figure 11-15. clocked seri al interface block diagram f xx /2 15 f xx /2 14 f xx /2 12 f xx /2 10 f xx /2 8 f xx /2 6 f xx /2 4 sckn sin sckn son intcsin control signal transmit data control serial clock controller clock start/stop control & clock phase control interrupt controller selector transmission control so selection so latch transmit data buffer register n (sotbn) shift register n (sion) remarks 1. n = 0, 1 2. f xx : internal system clock 11.3.3 control registers (1) clocked serial interface mode registers 0, 1 (csim0, csim1) the csimn register controls the operation of csin (n = 0, 1). these registers can be read or wr itten in 8-bit or 1-bit units. be sure to set bits 5 and 3 to 1 to 0. if they are set to 1, the operation is not guaranteed. caution to use csin, be sure to set the external pi ns related to the csin function to control mode and set the csicn register. then set the csi caen bit to 1 before setting the other bits.
chapter 11 serial interface function user's manual u14980ej2v1ud 323 <7> <6> 5 <4> 3 2 1 <0> address after reset csim0 csicae0 trmd0 0 dir0 0 0 0 csot0 fffff900h 00h csim1 csicae1 trmd1 0 dir1 0 0 0 csot1 fffff910h 00h bit position bit name function 7 csicaen (n = 0, 1) csi operation permission/prohibition specifies whether csin operation is enabled or disabled (n = 0, 1). 0: csin operation is disabled (son = low level, sckn = high level) 1: csin operation is enabled cautions 1. if csicaen is set to 0, the csin unit can be reset asynchronously. 2. if csicaen = 0, the csin unit is in a reset state. therefore, to operate csin, csicaen must be set to 1. 3. if the csicaen bit is changed from 1 to 0, all registers of the csin unit are initialized. to set csicaen to 1 again, the registers of the csin unit must be set again. 6 trmdn (n = 0, 1) transmission/reception mode control specifies the transmission/reception mode. 0: reception-only mode 1: transmission/reception mode if trmdn = 0, reception-only transfers are performed. in addition, the son pin output is fixed at low level. data recepti on is started by reading the sion register. if trmdn = 1, transmission/reception is started by writing data to the sotbn register. caution the trmdn bit can be overwritten only when csotn = 0. 4 dirn (n = 0, 1) transmit direction mode control specifies the transfer direction mode (msb or lsb). 0: the transfer data?s start bit is msb 1: the transfer data?s start bit is lsb caution the dirn bit can be overwritten only when csotn = 0. 0 csotn (n = 0, 1) csi status of transmission this is a transfer status display flag. 0: idle status 1: transfer execution status this flag is used to judge whether writing to the shift register (sion) is enabled or not when starting serial data transmissi on in transmission/reception mode (trmdn = 1) caution the csotn bit is reset when the csicaen bit is cleared (0).
chapter 11 serial interface function user's manual u14980ej2v1ud 324 (2) clocked serial interface clock select ion registers 0, 1 (csic0, csic1) the csicn register is an 8-bit register t hat controls the transmit operation of csin. these registers can be read or written in 8-bit units. caution the csicn register can be overwritte n when csicaen = 0 in the csimn register. (1/2) 7 6 5 4 3 2 1 0 address after reset csic0 0 0 0 ckp0 dap0 cks02 cks01 cks00 fffff901h 00h csic1 0 0 0 ckp1 dap1 cks12 cks11 cks10 fffff911h 00h bit position bit name function clock phase selection bit, data phase selection bit specifies the data transmission/reception timing for sckn. ckpn dapn operation mode 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sckn (input/output) sin capture son (output) 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sckn (input/output) sin capture son (output) 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sckn (input/output) sin capture son (output) 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sckn (input/output) sin capture son (output) 4, 3 ckpn, dapn (n = 0, 1)
chapter 11 serial interface function user's manual u14980ej2v1ud 325 (2/2) bit position bit name function input clock selection specifies the input clock. cksn2 cksn1 cksn0 input clock mode 0 0 0 f xx /2 15 master mode 0 0 1 f xx /2 14 master mode 0 1 0 f xx /2 12 master mode 0 1 1 f xx /2 10 master mode 1 0 0 f xx /2 8 master mode 1 0 1 f xx /2 6 master mode 1 1 0 f xx /2 4 master mode 1 1 1 external clock (sckn) slave mode 2 to 0 cksn2 to cksn0 (n = 0, 1) remark f xx : internal syst em clock frequency (a) baud rate baud rate (bps) cksn2 cksn1 cksn0 40 mhz operation 33 mhz operation 25 mhz operation 20 mhz operation 0 0 0 1,221 1,007 763 610 0 0 1 2,441 2,014 1,526 1,221 0 1 0 9,766 8,057 6,104 4,883 0 1 1 39,063 32,227 24,414 19,531 1 0 0 156,250 128,906 97,656 78,125 1 0 1 625,000 515,625 390,625 312,500 1 1 0 2,500,000 2,062,500 1,562,500 1,250,000
chapter 11 serial interface function user's manual u14980ej2v1ud 326 (3) serial i/o shift registers 0, 1 (sio0, sio1) the sion register is an 8-bit shift r egister that converts parallel data to serial data. if trmdn = 0 in the csimn register, the transfer is started by reading sion. except when a reset is input, the sion register becomes 00h even when the csicaen bit of the csimn register is cleared (0). these registers are read-only in 8-bit units. caution sion can be accessed only wh en the system is set to an idle state (csotn = 0 in the csimn register). 7 6 5 4 3 2 1 0 address after reset sio0 sio07 sio06 sio05 sio04 sio 03 sio02 sio01 sio00 fffff902h 00h sio1 sio17 sio16 sio15 sio14 sio 13 sio12 sio11 sio10 fffff912h 00h bit position bit name function 7 to 0 sion7 to sion0 (n = 0, 1) serial i/o shifts data in (reception) or shifts dat a out (transmission) beginning at the msb or the lsb side. (4) receive-only serial i/o shift registers 0, 1 (sioe0, sioe1) the sioen register is an 8-bit shift register that conver ts parallel data into serial data. a receive operation does not start even if the sioe n register is read while the trmd bit of t he csimn register is 0. therefore this register is used to read the value of the sion regist er (receive data) without st arting a receive operation. except when a reset is input, the sioen register becomes 00h even when the csicaen bit of the csimn register is cleared (0). these registers are read-only in 8-bit units. caution sioen can be accessed only when the syst em is set to an idle state (csotn = 0 in the csimn register). 7 6 5 4 3 2 1 0 address after reset sioe0 sioe07 sioe06 sioe05 sioe04 sioe03 sioe02 sioe01 sioe00 fffff903h 00h sioe1 sioe17 sioe16 sioe15 sioe14 sioe13 sioe12 sioe11 sioe10 fffff913h 00h bit position bit name function 7 to 0 sioen7 to sioen0 (n = 0, 1) serial i/o shifts data in (reception) beginning at the msb or the lsb side.
chapter 11 serial interface function user's manual u14980ej2v1ud 327 (5) clocked serial interface transmit bu ffer registers 0, 1 (sotb0, sotb1) the sotbn register is an 8-bit buffer register for storing transmit data. if transmission/reception mode is set (trmdn = 1 in the csimn register), a transmit operation is started by writing data to the sotbn register. when a reset is input, the sotbn register becomes 00h. these registers can be read or written in 8-bit units. caution sotbn can be accessed only when the system is set to an idle state (csotn = 0 in the csimn register). 7 6 5 4 3 2 1 0 address after reset sotb0 sotb07 sotb06 sotb 05 sotb04 sotb03 sotb02 sotb01 sotb00 fffff904h 00h sotb1 sotb17 sotb16 sotb 15 sotb14 sotb13 sotb12 sotb11 sotb10 fffff914h 00h bit position bit name function 7 to 0 sotbn7 to sotbn0 (n = 0, 1) serial i/o writes transmit data.
chapter 11 serial interface function user's manual u14980ej2v1ud 328 11.3.4 operation (1) transfer mode csin transmits and receives data in three lines: 1 clock line and 2 data lines. in reception-only mode (trmdn = 0 in the csimn re gister), the transfer is started by reading the sion register (n = 0, 1). the sioen register must be read wh en the sion register is read without reception being started. in transmission/reception mode (trmdn = 1 in the csimn r egister), the transfer is started by writing data to the sotbn register. once transfer has started, when an 8-bit transfer of csin ends, the csotn bit of the csimn register becomes 0, and transfer stops automatically. also, when the transfer ends, a transmission/reception completion interrupt (intcsin) is generated. cautions 1. when csotn = 1 in the csimn register , the control registers a nd data registers should not be accessed. 2. if transmit data is writte n to the sotbn register and the trmdn bit of the csimn register is changed from 0 to 1, seria l transfer is not performed. (2) serial clock (a) when internal clock is selected as the serial clock if reception or transmission is started, a serial clock is output from the sckn pin, and the data of the sin pin is taken into the sion register sequentially or dat a is output to the son pin sequentially from the sion register at the timing when the dat a has synchronized with the serial clock in accordance with the setting of the ckpn and dapn bits of the csicn register (n = 0, 1). (b) when external clock is selected as the serial clock if reception or transmission is started, the data of the sin pin is taken into the sion register sequentially or output to the son pin sequentially in synchronization with the serial clock that has been input to the sckn pin following transmission/reception startup in accordance with the setting of the ckpn and dapn bits of the csicn register (n = 0, 1). if serial clock is input to the sckn pin when neither reception nor transmission is started, shift operation will not be executed.
chapter 11 serial interface function user's manual u14980ej2v1ud 329 figure 11-16. transfer timing (a) when trmdn = 1, dirn = 0, ckpn = 0, and dapn = 0 10101010 1 0101010 (aah) (55h) (write 55h to sotbn) 55h (transmission data) csotn bit sckn reg-r/w sotbn sion sin son intcsin interrupt abh 56h adh b5h 6ah d5h aah 5ah remark n = 0, 1 (b) when trmdn = 1, dirn = 0, ckpn = 0, and dapn = 1 10101010 1 0101010 (aah) (55h) (write 55h to sotbn) 55h (transmission data) csotn bit sckn reg-r/w sotbn sion sin son intcsin interrupt abh 56h adh b5h 6ah d5h aah 5ah remark n = 0, 1
chapter 11 serial interface function user's manual u14980ej2v1ud 330 figure 11-17. clock timing (a) when ckpn = 0 and dapn = 0 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (b) when ckpn = 1 and dapn = 0 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (c) when ckpn = 0 and dapn = 1 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (d) when ckpn = 1 and dapn = 1 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 remark n = 0, 1
chapter 11 serial interface function user's manual u14980ej2v1ud 331 11.3.5 output pins (1) sckn pin when csin operation is disabled (csicaen = 0) , the sckn pin output state is as follows. ckpn sckn pin output 0 fixed at high level 1 fixed at low level remarks 1. when the ckpn bit is overwritt en, the sckn pin output changes. 2. n = 0, 1 (2) son pin when csin operation is disabled (csicaen = 0), the son pin output state is as follows. trmdn dapn dirn son pin output 0 fixed at low level 0 son latch value (low level) 0 sotbn7 value 1 1 1 sotbn0 value remarks 1. if any of the trmdn, dapn, and dirn bits is overwritten, the son pin output changes. 2. n = 0, 1 3. : don?t care
chapter 11 serial interface function user's manual u14980ej2v1ud 332 11.3.6 system configuration example csin performs 8-bit length data transfer using three types of signal lines: a serial clock (sckn), serial input (sin), and serial output (son). this is effective when connecti ng peripheral i/o that incorpor ates a conventional clocked serial interface, or a display controller to the v850e/ma2 (n = 0, 1). when connecting the v850e/ma2 to several devices, lines for handshake are required. since the first communication bit can be selected as an msb or lsb, communication with various devices can be achieved. figure 11-18. system configuration example of csi sck so si port (interrupt) port sck si so port port (interrupt) (3-wire serial i/o master cpu slave cpu 3-wire serial i/o)
333 user's manual u14980ej2v1ud chapter 12 a/d converter 12.1 features { analog input: 4 channels { 10-bit a/d converter { on-chip a/d conversion result register (adcr0 to adcr3) 10 bits 4 { a/d conversion trigger mode a/d trigger mode timer trigger mode { successive approximation method 12.2 configuration the a/d converter of the v850e/ma2 adopts the successive ap proximation method, and uses a/d converter mode registers 0, 1, 2 (adm0, adm1, adm2 ), and the a/d conversion result regi ster (adcr0 to adcr3) to perform a/d conversion operations. (1) input circuit the input circuit selects the analog input (ani0 to an i3) according to the mode set by the adm0 and adm1 registers and sends the input to the sample and hold register. (2) sample and hold circuit the sample and hold circuit samples each of the analog input signals sequentially sent from the input circuit, and sends them to the voltage comparator. this circui t also holds the sampled analog input signal during a/d conversion. (3) voltage comparator the voltage comparator compares the analog input signal with the output volt age of the series resistor string voltage tap. (4) series resistor string the series resistor string is used to gen erate voltages to match analog inputs. the series resistor string is connect ed between the reference voltage pin (av ref ) for the a/d converter and the gnd pin (av ss ) for the a/d converter. to make 1,024 equal voltage steps between these 2 pins, it is configured from 1,023 equal resistors and 2 re sistors with 1/2 of t he resistance value. the voltage tap of the series resist or string is selected by a tap sele ctor controlled by a successive approximation register (sar).
chapter 12 a/d converter 334 user's manual u14980ej2v1ud (5) successive approximation register (sar) the sar is a 10-bit register that sets series resistor string voltage tap data, whose values match analog input voltage values, 1 bit at a time starti ng from the most significant bit (msb). if data are set in the sar all the way to the least si gnificant bit (lsb) (a/d conversion completed), the contents of that sar (conversion results) are held in t he a/d conversion result register (adcrn). when all the specified a/d conversion oper ations have been completed, an a/ d conversion end interrupt (intad) occurs. (6) a/d conversion result register (adc rn: a/d conversion result register n) the adcr is a 10-bit register which holds a/d conversion results. each time a/d conversion is completed, conversion results are loaded from the su ccessive approximation register (sar). reset input sets this register to 0000h. (7) controller the controller selects the analog inpu t, generates the sample and hold ci rcuit operation timing, and controls the conversion trigger according to the mo de set by the adm0 and adm1 registers. (8) ani0 to ani3 pins these are 4-channel analog input pins for the a/d c onverter. they input the analog signals to be a/d converted. caution make sure that the voltag es input to ani0 to ani3 do not exceed the rated values. if a voltage higher than av dd or lower than av ss (even within the range of the absolute maximum ratings) is input to a channel, the c onversion value of the ch annel is undefined, and the conversion values of the othe r channels may also be affected. (9) av ref pin this is the pin for inputting the reference voltage of the a/d converter. it converts signals input to the anin pin to digital signals based on the voltage applied between av ref and av ss . in the v850e/ma2, the av ref pin functions alternately as the av dd pin. it is therefore impossible to set voltage separately for the av ref pin and the av dd pin.
chapter 12 a/d converter 335 user's manual u14980ej2v1ud figure 12-1. block diag ram of a/d converter ani0 ani1 ani2 ani3 intm000 intm001 intm010 intm011 intad input circuit adm0 (8) 8 voltage comparator sar (10) adcr0 adcr1 adcr2 adcr3 10 10 10 90 internal bus tap selector av dd/ av ref r/2 r r/2 series resitor string 70 adm1 (8) 70 av ss 8 adm2 (8) 70 8 controller sample & hold circuit f xx /2 remark f xx : internal system clock cautions 1. if there is noise at the analog input pins (ani0 to ani3) or at the reference voltage input pin (av ref ), that noise may generate an illegal conversion result. software processing will be needed to avoid a negative effect on the system from this illegal conversion result. an example of this softwar e processing is shown below. ? take the average result of a number of a/d conversions and use that as the a/d conversion result. ? execute a number of a/d conversions con secutively and use those results, omitting any exceptional results that may have been obtained. ? if an a/d conversion result that is judged to have genera ted a system malfunction is obtained, be sure to recheck the system malfunction before performing malfunction processing. 2. do not apply a voltage outside the av ss to av ref range to the pins that are used as a/d converter input pins.
chapter 12 a/d converter 336 user's manual u14980ej2v1ud 12.3 control registers (1) a/d converter mode register 0 (adm0) the adm0 register is an 8-bit regist er which executes the selection of th e analog input pin, specification of operation mode, and conversion operations. this register can be read/written in 8- or 1-bit units. however, when the data is written to the adm0 register during an a/d conversion operation, the conversion oper ation is initialized and conversion is executed from the beginning. bit 6 cannot be written to and writing executed is ignored. cautions 1. when the adce bit is 1 in the timer trigger mode, the tr igger signal standby state is set. to clear the adce bit, write ?0? or reset. in the a/d trigger mode, the conversion trigge r is set by writing 1 to the adce bit. after the operation, when the mode is changed to the timer trigger mode without clearing the adce bit, the trigger input standby state is set immediately after the register is changed. 2. there are 10 clocks between the beginni ng of conversion and when the adcs bit becomes 1.
chapter 12 a/d converter 337 user's manual u14980ej2v1ud address fffff200h <7> adce adm0 <6> adcs 5 bs 4 ms 3 0 2 anis2 1 anis1 0 anis0 after reset 00h bit position bit name function 7 adce convert enable enables or disables a/d conversion operation. 0: disabled 1: enabled 6 adcs converter status indicates the status of a/d converter. this bit is read only. 0: stops 1: operates 5 bs buffer select specifies buffer mode in the select mode. 0: 1-buffer mode 1: 4-buffer mode 4 ms mode select specifies operation mode of a/d converter. 0: scan mode 1: select mode analog input select specifies analog input pin to a/d convert. select mode scan mode anis2 anis1 anis0 a/d trigger mode timer trigger mode a/d trigger mode timer trigger mode note 0 0 0 ani0 ani0 ani0 1 0 0 1 ani1 ani1 ani0, ani1 2 0 1 0 ani2 ani2 ani0 to ani2 3 0 1 1 ani3 ani3 ani0 to ani3 4 other than above setting pr ohibited setting prohibited 2 to 0 anis2 to anis0 note in the timer trigger mode (4-trigger mode) dur ing the scan mode, because the scanning sequence of the ani0 to ani3 pins is specified by the sequ ence in which the match signals are generated from the compare register, the number of trigger inputs should be specified instead of specifying a certain analog input pin.
chapter 12 a/d converter 338 user's manual u14980ej2v1ud (2) a/d converter mode register 1 (adm1) the adm1 register is an 8-bit register which specif ies the conversion operation time and trigger mode. this register can be read/written in 8-bit units. howeve r, when the data is written to the adm1 register during an a/d conversion operation, the conv ersion operation is initialized and conversion is executed from the beginning. cautions 1. it takes the followin g number of clocks from trigger input to completion of a/d conversion, in addition to th e clocks specified using the fr 2 to fr0 bits. (refer to 12.7.6 supplementary informati on on a/d conversion time.) in a/d trigger mode: 11 to 13 clocks (9 to 11 cl ocks + 2 clocks) in timer trigger mode: 7 to 9 clocks (5 to 7 cl ocks + 2 clocks) 2. in the timer trigger mode, be sure to in put the trigger at an in terval longer than the number of clocks specified using the fr2 to fr 0 bits. (refer to 12.7.2 timer trigger interval.) address fffff201h 7 0 adm1 6 trg2 5 trg1 4 trg0 3 0 2 fr2 1 fr1 0 fr0 after reset 07h bit position bit name function trigger mode specifies trigger mode. trg2 trg1 trg0 trigger mode 0 0 0/1 a/d trigger mode 0 1 0 timer trigger mode (1-trigger mode) 0 1 1 timer trigger mode (4-trigger mode) other than above setting prohibited 6 to 4 trg2 to trg0 frequency specifies conversion operation ti me. these bits control conversion time to be same value irrespective of oscillation frequency. conversion operation time note fr2 fr1 fr0 number of conversion clock f xx = 40 mhz f xx = 33 mhz 0 0 0 96 setting prohibited setting prohibited 0 0 1 144 setting prohibited setting prohibited 0 1 0 192 setting prohibited 5.82 s 0 1 1 240 6.00 s 7.27 s 1 0 0 336 8.40 s 10.18 s 1 0 1 384 9.60 s setting prohibited 1 1 0 480 setting prohibited setting prohibited 1 1 1 672 setting prohibited setting prohibited 2 to 0 fr2 to fr0 note figures in the conversion operation time are target values. set the conversion operation time to 5 to 10 s. remark f xx = internal system clock
chapter 12 a/d converter 339 user's manual u14980ej2v1ud (3) a/d converter mode register 2 (adm2) the adm2 register is an 8-bit register that cont rols the reset and clock of the a/d converter. this register can be read/written in 8- or 1-bit units. caution because adcae = 0 after reset release, the a/d converter enters th e reset state. when operating the a/d converter, be sure to writ e to the adm0 and adm1 registers after setting the adcae bit of the adm2 register to 1 (it is impossible to write to the adm0 and adm1 registers when adcae = 0). moreover, when the adcae bit is set to 0, all registers related to the a/d converter are initialized. address fffff202h 7 0 adm2 6 0 5 0 4 0 3 0 2 0 1 0 <0> adcae after reset 00h bit position bit name function 0 adcae clock action enable controls a/d converter operation. 0: clock supply to the a/d converter is stopped, the a/d converter is in the reset state 1: the clock is supplied to the a/d converter, a/d converter operation is enabled
chapter 12 a/d converter 340 user's manual u14980ej2v1ud (4) a/d conversion result registers (adcr0 to adcr3, adcr0h to adcr3h) the adcrn register is a 10-bit regist er holding the a/d conversion results. there are four 10-bit registers. these registers are read-only in 16- or 8-bit units. duri ng the 16-bit access, the adcrn register is specified, and during higher 8-bit access, the adcrnh register is specified (n = 0 to 3). when reading the 10-bit data of a/d c onversion results from the adcrn register, only the lower 10 bits are valid and the higher 6 bits are always read as 0. 15 0 adcrn address fffff210h to fffff216h after reset 0000h 14 0 13 0 12 0 11 0 10 0 9 ad n9 8 ad n8 7 ad n7 6 ad n6 5 ad n5 4 ad n4 3 ad n3 2 ad n2 1 ad n1 0 ad n0 adcrnh address fffff220h to fffff223h after reset 00h 7 ad n9 6 ad n8 5 ad n7 4 ad n6 3 ad n5 2 ad n4 1 ad n3 0 ad n2 remark n = 0 to 3 the correspondence between each analog input pin and the adcrn register (except the 4-buffer mode) is shown below. analog input pin adcrn register ani0 adcr0, adcr0h ani1 adcr1, adcr1h ani2 adcr2, adcr2h ani3 adcr3, adcr3h
chapter 12 a/d converter 341 user's manual u14980ej2v1ud the relationship between the analog voltage input to the analog input pins (ani0 to ani3) and the a/d conversion result (of the a/d conversion resu lt register (adcrn)) is as follows: 0.5) 1,024 av v ( int adcr ref in + = or, 1,024 av 0.5) (adcr v 1,024 av 0.5) (adcr ref in ref + < ? int( ): function that returns the integer of the value in ( ) v in : analog input voltage av ref : av ref pin voltage adcr: value of a/d conversion result register (adcrn) figure 12-2 shows the relationship between the ana log input voltage and the a/d conversion results. figure 12-2. relationship between analog input voltage and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av ref 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion results (adcrn) remark n = 0 to 3
chapter 12 a/d converter 342 user's manual u14980ej2v1ud 12.4 a/d converter operation 12.4.1 basic operation of a/d converter a/d conversion is executed in the following order. (1) the adcae bit of the adm2 register is set (1). (2) the selection of the analog input and specification of the operation mode, trigger mode, etc. should be specified using the adm0 and adm1 registers note 1 . when the adce bit of the adm0 register is set (1), a/d conversion starts in a/d trigger mode. in the timer trigger mode, the trigger standby state note 2 is set. (3) the voltage generated from the vo ltage tap of the series resistor st ring and analog input are compared by the comparator. (4) when the comparison of the 10 bits ends, the conver sion results are stored in the adcrn register. when a/d conversion has been performed fo r the specified number of times, the a/d conversion end interrupt (intad) is generated (n = 0 to 3). notes 1. when the adm0 to adm2 registers are changed during the a/d conversi on operation, the a/d conversion operation before the change is stopped and the conversion results are not stored in the adcrn register. 2. during the timer trigger mode, if the adce bit of the adm0 register is set to 1, the mode changes to the trigger standby state. t he a/d conversion operation is start ed by the trigger signal, and the trigger standby state is returned wh en the a/d conversion operation ends.
chapter 12 a/d converter 343 user's manual u14980ej2v1ud 12.4.2 operation mode and trigger mode various conversion operations can be specified for the a/ d converter by specifying the operation mode and trigger mode. the operation mode and trigger mode are set by the adm0 and adm1 registers. the following shows the relationship betwe en the operation mode and trigger mode. setting value trigger mode operation mode adm0 adm1 analog input 1 buffer xx010xxxb 000x0xxxb select 4 buffers xx110xxxb 000x0xxxb a/d trigger scan xxx00xxxb 000x0xxxb 1 buffer xx010xxxb 00100xxxb select 4 buffers xx110xxxb 00100xxxb 1 trigger scan xxx00xxxb 00100xxxb 1 buffer xx010xxxb 00110xxxb select 4 buffers xx110xxxb 00110xxxb timer trigger 4 trigger scan xxx00xxxb 00110xxxb ani0 to ani3 (1) trigger mode there are two types of trigger modes which serve as the start timing of a/d conversion processing: a/d trigger mode and timer trigger mode. the timer trigge r mode consists of the 1-trigger mode and 4-trigger mode as the sub-trigger mode. these trig ger modes are set by the adm1 register. (a) a/d trigger mode this mode starts the conversion timing of the analog input set to pins ani0 to ani3, and by setting the adce bit of the adm0 register to 1, starts a/d conversion. (b) timer trigger mode specifies the conversion timing of the analog input set for the ani0 to ani3 pins using the values set to the timer c compare register. this register creates the analog input conversion timing by generating the match interrupts (intm000, intm001, intm010, intm011) of the four capture/ compare registers (ccc00, ccc01, ccc10, ccc11) connected to the 16-bit timer c (tmc0, tmc1). moreover, because the match interrupts (intm000, intm001, intm010, intm011) are also used as exte rnal pin interrupts (intp000, intp001, intp010, intp011), the analog input conversion timing is generat ed even when external pin interrupts are input. there are two types of sub-trigger modes : 1-trigger mode and 4-trigger mode. ? 1-trigger mode a mode which uses one match interrupt from ti mer c as the a/d conversion start timing. ? 4-trigger mode a mode which uses four match interrupts from timer c as the a/d conversion start timing.
chapter 12 a/d converter 344 user's manual u14980ej2v1ud (2) operation mode there are two types of operation modes which set the an i0 to ani3 pins: select mode and scan mode. the select mode has a sub-mode that consists of 1-buffe r mode and 4-buffer mode. these modes are set by the adm0 register. (a) select mode in this mode, one analog input specified by the adm0 register is a/d converted. the conversion results are stored in the adcrn register corresponding to the analog input (anin). for this mode, the 1-buffer mode and 4-buffer mode are provided for storing the a/d conversion results (n = 0 to 3). ? 1-buffer mode in this mode, one analog input specified by the adm0 register is a/d conver ted. the conversion results are stored in the adcrn register correspon ding to the analog input (anin). the anin and adcrn register correspond one to one, and an a/ d conversion end interrupt (intad) is generated each time one a/d conversion ends.
chapter 12 a/d converter 345 user's manual u14980ej2v1ud figure 12-3. select mode operat ion timing: 1-buffer mode (ani1) ani1 (input) a/d conversion data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 (ani1) data 6 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 (ani1) adcr1 register intad interrupt conversion start (adm0 register setting) adce bit set adce bit set adce bit set adce bit set conversion start (adm0 register setting) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter adcrn register analog input
chapter 12 a/d converter 346 user's manual u14980ej2v1ud ? 4-buffer mode in this mode, one analog input is a/d converted f our times and the results are stored in the adcr0 to adcr3 registers. the a/d conversion end interr upt (intad) is generated when the four a/d conversions end. figure 12-4. select mode operat ion timing: 4-buffer mode (ani2) ani2 (input) a/d conversion data 1 (ani2) data 2 (ani2) data 3 (ani2) data 4 (ani2) data 5 (ani2) data 6 (ani2) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani2) adcr0 data 2 (ani2) adcr1 data 3 (ani2) adcr2 data 4 (ani2) adcr3 data 5 (ani2) adcr0 adcrn register intad interrupt conversion start (adm0 register setting) conversion start (adm0 register setting) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter adcrn register analog input
chapter 12 a/d converter 347 user's manual u14980ej2v1ud (b) scan mode in this mode, the analog inputs specified by the ad m0 register are selected sequentially from the ani0 pin, and a/d conversion is execut ed. the a/d conversion results ar e stored in the adcrn register corresponding to the analog input (n = 0 to 3). w hen the conversion of the s pecified analog input ends, the a/d conversion end interr upt (intad) is generated. figure 12-5. scan mode operation ti ming: 4-channel scan (ani0 to ani3) ani3 (input) ani0 (input) ani1 (input) ani2 (input) a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani0) adcr0 data 2 (ani1) adcr1 data 3 (ani2) adcr2 data 4 (ani3) adcr3 data 5 (ani0) adcr0 adcrn register intad interrupt conversion start (adm0 register setting) conversion start (adm0 register setting) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter adcrn register analog input
chapter 12 a/d converter 348 user's manual u14980ej2v1ud 12.5 operation in a/d trigger mode when the adce bit of the adm0 register is set to 1, a/d conversion is started. 12.5.1 select mode operation in this mode, the analog input specified by the adm0 regi ster is a/d converted. the conversion results are stored in the adcrn register corresponding to the analog input. in the select mode, the 1-buffer mode and 4-buffer mode are supported according to the storing method of the a/d conversion results (n = 0 to 3). (1) 1-buffer mode (a/d trigger select: 1-buffer) in this mode, one analog input is a/d converted once . the conversion results are stored in one adcrn register. the analog input and adcrn register correspond one to one. each time an a/d conversion is executed, an a/d conv ersion end interrupt (intad) is generated and the ad conversion completes. analog input a/d conversion result register anin adcrn if 1 is written in the adce bit of the adm0 register, a/d conversion can be restarted. this mode is most appropriate for applications in which th e results of each first time a/d conversion are read. figure 12-6. example of 1-buffer mode (a /d trigger select 1-buffer) operation ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter adm0 (1) the adce bit of adm0 is set to 1 (enable) (2) ani2 is a/d converted (3) the conversion result is stored in adcr2 (4) the intad interrupt is generated
chapter 12 a/d converter 349 user's manual u14980ej2v1ud (2) 4-buffer mode (a/d trigger select: 4-buffer) in this mode, one analog input is a/d converted four times and the results are stored in the adcr0 to adcr3 registers. when the 4th a/d conv ersion ends, an a/d conversion end inte rrupt (intad) is generated and the a/d conversion is stopped. analog input a/d conversion result register anin adcr0 anin adcr1 anin adcr2 anin adcr3 if 1 is written in the adce bit of the adm0 register, a/d conversion can be restarted. this mode is suitable for applications in which the average of a/d conversion result is calculated. figure 12-7. example of 4-buffer mode (a /d trigger select 4-buffer) operation ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter adm0 ( 4) (1) the adce bit of adm0 is set to 1 (enable) (6) ani3 is a/d converted (2) ani3 is a/d converted (7) the conversion result is stored in adcr2 (3) the conversion result is stored in adcr0 (8) ani3 is a/d converted (4) ani3 is a/d converted (9) the conversion result is stored in adcr3 (5) the conversion result is stored in adcr1 (10) the intad interrupt is generated
chapter 12 a/d converter 350 user's manual u14980ej2v1ud 12.5.2 scan mode operations in this mode, the analog inputs specified by the adm0 re gister are selected sequentially from the ani0 pin, and a/d conversion is executed. the a/d conversion results are stored in the adcrn register corresponding to the analog input (n = 0 to 3). when the conversion of all the specified analog input ends , the a/d conversion end inte rrupt (intad) is generated, and a/d conversion is stopped. analog input a/d conversion result register ani0 adcr0 anin note adcrn note set by the ani0 to ani2 bits of the adm0 register. if 1 is written in the adce bit of the adm0 register, a/d conversion can be restarted. this mode is most appropriate for applications in whic h multiple analog inputs are constantly monitored. figure 12-8. example of scan m ode (a/d trigger scan) operation ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter adm0 (1) the adce bit of adm0 is set to 1 (enable) (6) ani2 is a/d converted (2) ani0 is a/d converted (7) the conversion result is stored in adcr2 (3) the conversion result is stored in adcr0 (8) ani3 is a/d converted (4) ani1 is a/d converted (9) the conversion result is stored in adcr3 (5) the conversion result is stored in adcr1 (10) the intad interrupt is generated . . . . . .
chapter 12 a/d converter 351 user's manual u14980ej2v1ud 12.6 operation in timer trigger mode conversion timings for up to four-channel analog inputs (ani0 to ani3) can be set for the a/d converter using the interrupt signal output from the tmc compare register. two 16-bit timers (tmc0, tmc1) and four capture/co mpare registers (ccc00, ccc0 1, ccc10, cc11) are used for the timer to specify the analog conversion trigger. the following two modes are provided according to the value set in the tmcc01 or tmcc11 register. (1) 1-shot mode to use the 1-shot mode, set the ostn bit of the tm ccn1 register (overflow stop mode) to 1 (n = 0, 1). when tmc overflows, 0000h is held, and counter operat ion stops. thereafter, tmcn does not output the match interrupt signal (a/d conversion trigger) of the compare register, and the a/d converter enters the a/d conversion standby state. the tmcn count operation restarts when the tmccen bit of the tmccn0 register is set to 1. the 1-shot mode is used when the a/d c onversion cycle is longer than the tmc cycle. (n = 0, 1). (2) loop mode to use the loop mode, set the ost bit of the tmcc n1 register to 0 (free running mode) (n = 0, 1). when tmcn overflows, the tmcn star ts counting from 0000h again, and the match interrupt signal (a/d conversion trigger) of the compare register is repeat edly output and a/d conversion is also repeated.
chapter 12 a/d converter 352 user's manual u14980ej2v1ud 12.6.1 select mode operation in this mode, an analog input (ani0 to ani3) specified by the adm0 register is a/d c onverted. the conversion results are stored in the adcrn register corresponding to t he analog input. in the select mode, the 1-buffer mode and 4-buffer mode are provided according to the storing me thod of the a/d conversion results (n = 0 to 3). (1) 1-buffer mode operation (tim er trigger select: 1-buffer) in this mode, one analog input is a/d converted once and the conversion results are stored in one adcrn register. there are two modes in the 1-buffer mode: 1-trigger mode and 4-trigger mode, according to the number of triggers. (a) 1-trigger mode (timer trigge r select: 1 buffer, 1 trigger) in this mode, one analog input is a/d converted once using the trigge r of the match interrupt signal (intm000) and the results are stor ed in one adcrn register. an a/d conversion end interrupt (intad) is generated for each a/d conversion and a/d conversion (n = 0 to 3) is stopped. trigger analog input a/d conversion result register intm000 interrupt anin adcrn in 1-shot mode, a/d conversion stops after one conver sion. to restart a/d conversion, set the tmcce0 bit of the tmcc00 register to 1. when set to the loop mode, unless the adce bit of t he adm0 register is set to 0, a/d conversion is repeated each time a match interrupt is generated. figure 12-9. example of 1-trigger mode (timer trigger select 1-buffer 1-trigger) operation ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter intm000 (1) the adce bit of adm0 is set to 1 (enable) (2) the ccc00 compare is generated (3) ani1 is a/d converted (4) the conversion result is stored in adcr1 (5) the intad interrupt is generated
chapter 12 a/d converter 353 user's manual u14980ej2v1ud (b) 4-trigger mode (timer trigge r select: 1-buffer, 4-trigger) in this mode, one analog input is a/d converted using four match interrupt signals (intm000, intm001, intm010, intm011) as triggers and the results are st ored in one adcrn register. the a/d conversion end interrupt (intad) is generated wit h each a/d conversion, and the adcs bit of the adm0 register is reset (0). the results of one a/d conversion are he ld in the adcrn register until the next a/d conversion ends. perform transmission of the conversion results to the memory and other operations using the intad interrupt after each a/d conversion ends (n = 0 to 3). trigger analog input a/d conversion result register intm000 interrupt anin adcrn intm001 interrupt anin adcrn intm010 interrupt anin adcrn intm011 interrupt anin adcrn in 1-shot mode, a/d conversion stops after four conversions. to restart a/d conversion, set the tmccen bit of the tmccn0 register to 1 to restart t he tmcn. when the first match interrupt after tmcn is restarted is generated, the adcs bit is set (1) and a/d conversion is started (n = 0, 1). when set to the loop mode, unless the adce bit of t he adm0 register is set to 0, a/d conversion is repeated each time a match interrupt is generated. the match interrupts (intm000, in tm001, intm010, intm011) can be generated in any order. also, even in cases where the same trigger is input continuously, it is received as a trigger. figure 12-10. example of 4-trigger mode (timer trigger select 1-buffer 4-trigger) operation ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter intm000 intm001 intm010 intm011 no particular order ( 4) ( 4) (1) the adce bit of adm0 is set to 1 (enable) (10) the ccc11 compare is generated (random) (2) the ccc10 compare is generated (r andom) (11) ani2 is a/d converted (3) ani2 is a/d converted (12) the conversion result is stored in adcr2 (4) the conversion result is stored in adcr2 (13) the intad interrupt is generated (5) the intad interrupt is generated (14) the ccc00 compare is generated (random) (6) the ccc01 compare is generated (r andom) (15) ani2 is a/d converted (7) ani2 is a/d converted (16) the conversion result is stored in adcr2 (8) the conversion result is stored in adcr2 (17) the intad interrupt is generated (9) the intad interrupt is generated
chapter 12 a/d converter 354 user's manual u14980ej2v1ud (2) 4-buffer mode operation (tim er trigger select: 4-buffer) in this mode, a/d conversion of one analog input is executed four times, and the results are stored in the adcr0 to adcr3 registers. there are two 4-buffer modes: 1-trigger mode and 4-trigger mode, according to the number of triggers. this mode is suitable for applications in which the av erage of the a/d conversi on result is calculated. (a) 1-trigger mode in this mode, one analog input is a/d converted four times using the ma tch interrupt signal (intm000) as a trigger, and the results are stored in adcr0 to ad cr3 registers. the a/d conversion end interrupt (intad) is generated when the four a/d conv ersions end and a/d conversion is stopped. trigger analog input a/d conversion result register intm000 interrupt anin adcr0 intm000 interrupt anin adcr1 intm000 interrupt anin adcr2 intm000 interrupt anin adcr3 if the one-shot mode is set and the tmcce0 bit of t he tmcc00 register is set to 1, and if the match interrupt occurs less than four times, the intad inte rrupt does not occur but is in the standby status. figure 12-11. example of 1-trigger mode (timer trigger select 4-buffer 1-trigger) operation ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter intm000 ( 4) ( 4) (1) the adce bit of adm0 is set to 1 ( enable) (8) the ccc00 compare is generated (2) the ccc00 compare is generated (9) ani2 is a/d converted (3) ani2 is a/d converted (10) the conversion result is stored in adcr2 (4) the conversion result is stored in a dcr0 (11) the ccc00 compare is generated (5) the ccc00 compare is generated (12) ani2 is a/d converted (6) ani2 is a/d converted (13) the conversion result is stored in adcr3 (7) the conversion result is stored in adcr1 (14) the intad interrupt is generated
chapter 12 a/d converter 355 user's manual u14980ej2v1ud (b) 4-trigger mode in this mode, one analog input is a/d converted using four match interrupt signals (intm000, intm001, intm010, intm011) as triggers and the results are stored in four adcrn register s. the a/d conversion end interrupt (intad) is generated when a/d conver sion ends, the adcs bit is reset (0), and a/d conversion is stopped. trigger analog input a/d conversion result register intm000 interrupt anin adcr0 intm001 interrupt anin adcr1 intm010 interrupt anin adcr2 intm011 interrupt anin adcr3 in 1-shot mode, a/d conversion stops after four co nversions. to restart the a/d conversion, set the tmccen bit of the tmccn0 register to 1 to restart t he tmcn. when the first match interrupt after tmcn is restarted is generated, the adcs bit is set (1) and a/d conversion is started (n = 0, 1). when set to the loop mode, unless the adce bit of t he adm0 register is set to 0, a/d conversion is repeated each time a match interrupt is generated. the match interrupts (intm000, intm001, intm010, intm011) can be generated in any order, and the conversion results are stored in t he adcrn register corresponding to the input trigger. also, even in cases where the same trigger is input continuously, it is received as a trigger. figure 12-12. example of 4-trigger mode (timer trigger select 4-buffer 4-trigger) operation ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter intm000 intm001 intm010 intm011 no particular order no particular order ( 4) (1) the adce bit of adm0 is set to 1 (enable) (8) the ccc10 compare is generated (random) (2) the ccc01 compare is generated (random) (9) ani2 is a/d converted (3) ani2 is a/d converted (10) the conversion result is stored in adcr2 (4) the conversion result is stored in adcr1 (11) the ccc00 compare is generated (random) (5) the ccc11 compare is generated (r andom) (12) ani2 is a/d converted (6) ani2 is a/d converted (13) the conversion result is stored in adcr0 (7) the conversion result is stored in adcr3 (14) the intad interrupt is generated
chapter 12 a/d converter 356 user's manual u14980ej2v1ud 12.6.2 scan mode operation in this mode, the analog inputs specified by the adm0 regi ster are selected sequentially from the ani0 pin and are a/d converted for the specified number of times using the match interrupt signal as a trigger. in the conversion operation, the analog input channels (ani0 to ani3) are a/d converted for the specified number of times. when the set number of a/d conversions ends , the a/d conversion end interr upt (intad) is generated and a/d conversion is stopped. there are two scan modes: 1-trigger mode and 4-tr igger mode, according to the number of triggers. this mode is most appropriate for applications in whic h multiple analog inputs are constantly monitored. (1) 1-trigger mode (timer tr iggers scan: 1-trigger) in this mode, analog inputs are a/d converted for the specified number of times using the match interrupt signal (intm000) as a trigger. the analog input and adcrn register correspond one to one. when all the a/d conversions specified have been e nded, the a/d conversion en d interrupt (intad) is generated and a/d conv ersion is stopped. trigger analog input a/d conversion result register intm000 interrupt ani0 adcr0 intm000 interrupt ani1 adcr1 intm000 interrupt ani2 adcr2 intm000 interrupt ani3 adcr3 when the match interrupt is generated after all the s pecified a/d conversions have ended, a/d conversion is restarted. in 1-shot mode, and when less than a specified number of match interrupts are generated, the intad interrupt is not generated and the standby state is set. figure 12-13. example of 1-trigger mode (t imer trigger scan 1-trigger) operation (a) setting when scanning ani0 to ani3 ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter intm000 (1) the adce bit of adm0 is set to 1 ( enable) (8) the ccc00 compare is generated (2) the ccc00 compare is generated (9) ani2 is a/d converted (3) ani0 is a/d converted (10) the conversion result is stored in adcr2 (4) the conversion result is stored in a dcr0 (11) the ccc00 compare is generated (5) the ccc00 compare is generated (12) ani3 is a/d converted (6) ani1 is a/d converted (13) the conversion result is stored in adcr3 (7) the conversion result is stored in adcr1 (14) the intad interrupt is generated
chapter 12 a/d converter 357 user's manual u14980ej2v1ud (2) 4-trigger mode in this mode, analog inputs are a/d converted for the number of times specified using the match interrupt signal (intm000, intm001, intm010, intm011) as a trigger. the analog input and adcrn register correspond one to one. when all the a/d conversions specified have ended, t he a/d conversion end inte rrupt (intad) is generated and a/d conversion is stopped. trigger analog input a/d conversion result register intm000 interrupt ani0 adcr0 intm001 interrupt ani1 adcr1 intm010 interrupt ani2 adcr2 intm011 interrupt ani3 adcr3 to restart a/d conversion in 1-shot mode, restart tm cn. if set to the loop mode and the adce bit of the adm0 register is 1, a/d conversion is restarted w hen a match interrupt is generated after conversion has ended. the match interrupt can be generated in any order. ho wever, because the trigger signal and the analog input correspond one to one, the scanning sequence is determined according to the order in which the match signals of the compare register are generated. figure 12-14. example of 4-trigger mode (t imer trigger scan 4-trigger) operation (a) setting when scanning ani0 to ani3 ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 a/d converter intm000 random intm001 intm010 intm011 (1) the adce bit of adm0 is set to 1 (enable) (8) the ccc00 compare is generated (random) (2) the ccc01 compare is generated (random) (9) ani0 is a/d converted (3) ani1 is a/d converted (10) the conversion result is stored in adcr0 (4) the conversion result is stored in adcr1 (11) the ccc10 compare is generated (random) (5) the ccc11 compare is generated (r andom) (12) ani2 is a/d converted (6) ani3 is a/d converted (13) the conversion result is stored in adcr2 (7) the conversion result is stored in adcr3 (14) the intad interrupt is generated
chapter 12 a/d converter 358 user's manual u14980ej2v1ud 12.7 precautions in operations 12.7.1 stopping conversion operation when the adce bit of the adm0 register is set to 0 dur ing a conversion operation, t he conversion operation stops and the conversion results are not stored in the adcrn register (n = 0 to 3). 12.7.2 timer trigger interval set the interval (input time interval) of the trigger in the timer trigger mode longer than the conversion time specified by the fr2 to fr0 bits of the adm1 register. (1) when interval = 0 when several triggers are input simultaneously, the analog input with the smaller anin pin number is converted. the other trigger signals input simultaneously are ignored, and the number of trigger input is not counted. take note, therefor e, that the saving of the result to t he adcrn register upon the generation of an interrupt is an abnormality (n = 0 to 3). (2) when 0 < interval < conversion operation time when the timer trigger is input during a conversion operation, the conversion operation is aborted and the conversion starts according to the last timer trigger input. when conversion operations are aborted, the conversion results are not stored in the adcrn register, and the number of trigger input are not coun ted. take note, therefore, that th e saving of the result to the adcrn register upon the generation of an interrupt is an abnormality (n = 0 to 3). (3) when interval = conversion operation time when a trigger is input concurrently with the end of conversion (the conversion complete signal and the trigger are in contention), although the number of triggers input are counted, an interrupt is generated, and the value at the end of conversion is correctly saved in the adcrn register, design should be performed so that the interval is greater th an the conversion operation time. 12.7.3 operation in standby mode (1) halt mode in this mode, a/d conversion continues. when this mode is released using the nmi input, the adm0 and adm1 registers and adcrn register hold the value (n = 0 to 3). (2) idle mode, software stop mode as clock supply to the a/d converter is stop ped, no conversion operations are performed. when these modes are released using the nmi input or maskable interrupt input (intp1x), the adm0 and adm1 registers and the adcrn register hold the value. however, when the idle or software stop mode is set during a conversion operation, the conversion operation is stopped. at this time, if the mode released using the nmi input or maskable interrupt input (i ntp1x), the conversion operation resumes, but the conversion result written to the adcrn register will become undefined (x = 00, 01, 10, n = 0 to 3).
chapter 12 a/d converter 359 user's manual u14980ej2v1ud 12.7.4 compare match interrupt when in timer trigger mode the compare register?s match inte rrupt becomes an a/d conversion star t trigger and starts the conversion operation. when this happens, the compare register?s matc h interrupt also functions as a compare register match interrupt for the cpu. in order to pr event match interrupts from the compare register for the cpu, disable interrupts by the mask bits (p00mk0, p00mk1, p01mk0, p01mk1) of t he interrupt control register (p00ic0, p00ic1, p01ic0, p01ic1). 12.7.5 reconversion operation in timer 1 trigger mode in the timer 1 trigger mode, a/d conver sion is started with the match interrupt signal (intm000) as the trigger. however, when interrupt sources which are non- triggers (intm001, intm010, intm011, intp001 note , intp010 note , intp011 note ) are generated during a/d conversion, after this a/d conversion ends normally, the same a/d conversion may start again (reconversion operation). however, the reconversion operation will not be performed unless non- trigger interrupt sources are g enerated under these conditions. note external interrupt signals also used as external capt ure trigger inputs of timer c (tmc0, tmc1) also trigger reconversion. (1) reconversion opera tion in the timer trigger sel ect 1 buffer 1 trigger mode when non-trigger interrupt sources are generated dur ing a/d conversion, the first a/d conversion ends normally, and the a/d conversion end interrupt (intad) is generated. the a/d conversion results are stored in the adcrn register. a restart ed a/d conversion is carried out norma lly, and the a/d conversion results are overwritten in the adcrn register. during reconver sion, the adcrn register can be read. after a/d conversion ends, the intad interrupt is generated, and a/d conversion stops. (2) reconversion operation in timer trigger select 4 buffer 1 trigger m ode, timer trigger scan 1 trigger mode a/d conversion is performed smoothl y until non-trigger interrupt sources are generated during conversion. when non-trigger interrupt sources are generated durin g a/d conversion, the current a/d conversion ends normally, and the a/d conversion re sults are stored in the adcrn register. after this, the same a/d conversion is performed, and the a/d conversion result s are overwritten in the adcrn register. during reconversion, the adcrn register can be read. a fter this, the remaining a/d conversion operations are performed normally, the a/d conversion end interrupt (intad) is generated, and a/d conversion stops. caution when non-trigger interrupt sources are ge nerated during the last a/ d conversion, the last a/d conversion ends normally, and the a/d con version end interrupt (int ad) is generated. after this, the same conversion as the last a/d conversion is pe rformed, the intad interrupt is generated, and a/d conversion stops. when reconversion operations occur, as conversion re sults are normal values, the effect on conversion will be minimized when using a methods in which the latest conversion values are acquired. however, if reconversion operations become abnormal, be sure to use the a/d trigger mode a nd start a/d conversion by setting the adce bit of the adm0 register in the interru pt servicing routine of the compare match interrupt of the timer.
chapter 12 a/d converter 360 user's manual u14980ej2v1ud 12.7.6 supplementary informa tion on a/d conversion time the time taken from trigger input to t he end of a/d conversion (t) is as follows. in a/d trigger mode (refer to figures 12-15 and 12-17 ): t = 9 to 11 clocks + number of clocks specifie d by the fr2 to fr0 bits of adm1 + 2 clocks in timer trigger mode (refer to figures 12-16 and 12-17 ): t = 5 to 7 clocks + number of clocks specifie d by the fr2 to fr0 bits of adm1 + 2 clocks figure 12-15. a/d trigger mode a/ d conversion time: when adm1 = 00h 7 to 9 clocks 9 to 11 clocks operation stopped (trigger input standby) sampling conversion of adn9 bit of adcrn register 2 clocks a/d conversion start f xx write signal adcs bit status remarks 1. f xx : internal system clock 2. n = 0 to 3 figure 12-16. timer trigger mode a/d co nversion time: when adm1 = 20h or 30h conversion of adn9 bit of adcrn register 5 to 7 clocks operation stopped (trigger input standby) sampling f xx interrupt signal (intm0ab) status a/d conversion start remarks 1. f xx : internal system clock 2. n = 0 to 3 ab: when adm1 = 20h, ab = 00, when adm1 = 30h, ab = 00, 01, 10, 11
chapter 12 a/d converter 361 user's manual u14980ej2v1ud figure 12-17. a/d conversion outline: one a/d conversion, fr0 to fr2 bits of adm1 register = 000 (96 clocks) sampling one a/d conversion number of clocks set using fr2 to fr0 bits of adm1 register (96 clocks) 2 clocks 4 clocks conversion of adn9 bit of adcrn register conversion of adn0 bit of adcrn register note f xx status intad interrupt note a/d conversion results (adcrn) can be read. remarks 1. f xx : internal system clock 2. n = 0 to 3
chapter 12 a/d converter 362 user's manual u14980ej2v1ud 12.8 how to read a/d converter characteristics table this section describes the terms related to the a/d converter. (1) resolution the minimum analog input voltage that can be recognized, i. e., the ratio of an analog input voltage to 1 bit of digital output is called 1 lsb (least significant bit). the ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as foll ows, independently of the resolution. 1%fsr = (maximum value of convertible analog input voltage ? minimum value of convertible analog input voltage)/100 = (av ref ? 0)/100 = av ref /100 where the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the overall error, independently of the resolution. (2) overall error this is the maximum value of the difference between an actually measured value and a theoretical value. it is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. the overall error in the characteristics t able does not include the quantization error. figure 12-18. overall error ideal line overall error 1 ...... 1 0 ...... 0 0av ref analog input digital output
chapter 12 a/d converter 363 user's manual u14980ej2v1ud (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog value is converted into a digital value. because the a/d converter converts ana log input voltages in a range of 1/2 lsb into the same digital codes, a quantization error is unavoidable. this error is not included in the overall error, zero-scale error, full-scale error, in tegral linearity error, or differential linearity error in the characteristics table. figure 12-19. quan tization error quantization error 1 ...... 1 0 ...... 0 0av ref analog input digital output 1/2 lsb 1/2 lsb (4) zero-scale error this is the difference between the ac tually measured analog input voltage and its theoretical value when the digital output changes from 0?000 to 0?001 (1/2 lsb). figure 12-20. zero-scale error av ref analog input (lsb) digital output (lower 3 bits) ideal line 111 ? 10123 100 011 010 001 000 zero-scale error
chapter 12 a/d converter 364 user's manual u14980ej2v1ud (5) full-scale error this is the difference between the ac tually measured analog input voltage and its theoretical value when the digital output changes from 1?110 to 0?111 (full scale ? 3/2 lsb). figure 12-21. full-scale error av ref analog input (lsb) digital output (lower 3 bits) 111 av ref ? 3 0 av ref ? 2av ref ? 1 100 011 010 000 full-scale error (6) differential linearity error ideally, the width to output a specific code is 1 lsb. this error indicates the difference between the actually measured value and its theoretical value when a specific code is output. figure 12-22. differential linearity error ideal width of 1 lsb differential linearity error 1 ...... 1 0 ...... 0 av ref analog input digital output
chapter 12 a/d converter 365 user's manual u14980ej2v1ud (7) integral linearity error this error indicates the extent to which the conversion ch aracteristics differ from the ideal linear relations. it indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. figure 12-23. integral linearity error 1 ...... 1 0 ...... 0 0av ref analog input digital output ideal line integral linearity error (8) conversion time this is the time required to obtain a digital output after an analog input voltage has been assigned. the conversion time in the characteristics table includes the sampling time. (9) sampling time this is the time for which the analog switch is on to load an analog voltage to the sample & hold circuit. figure 12-24. sampling time sampling time conversion time
user's manual u14980ej2v1ud 366 chapter 13 port functions 13.1 features ? input-only ports: 5 i/o ports: 74 ? alternately function as other peripheral i/o pins. ? input and output can be specified in 1-bit units.
chapter 13 port functions user's manual u14980ej2v1ud 367 13.2 port configuration the v850e/ma2 incorporates a total of 79 input/output ports (including 5 input-only ports) labeled ports 0 to 2, 4, 7, al, ah, dl, cs, ct, cm, cd, and bd. t he port configuration is shown below. port 0 p01 to p05 port 1 p11 p12 port 2 p20 p24 port 4 p40 to p45 port 7 p70 to p73 port al port ah pal0 to pal15 pah0 to pah8 port dl port cs port ct port cm pdl0 to pdl15 pcs0 pcs3 pcs4 pcs7 pct0 pct1 pct4 pct5 pcm0 to pcm4 port cd pcd0 to pcd3 port bd pbd0 pbd1
chapter 13 port functions user's manual u14980ej2v1ud 368 (1) function of each port the port functions of this product are shown below. 8-bit and 1-bit operations are possible on all ports, allowing various kinds of control to be performed. in addi tion to their port functions, these pins also function as internal peripheral i/o pins in the control mode . for the block types of each port, refer to (3) block diagram of port . port name pin name port function function in control mode block type port 0 p01 to p05 5-bit i/o real-time pulse unit (rpu) i/o external interrupt input dma controller input a, b, h port 1 p11, p12 2-bit i/o real-time pulse unit (rpu) input external interrupt input b port 2 p20, p24 1-bit input, 1-bit i/o nmi input external interrupt input dma controller output f, n port 4 p40 to p45 6-bit i/o serial interf ace i/o (uart0/csi0, uart1/csi1) g, h, m port 7 p70 to p73 4-bit input a/d converter input c port al pal0 to pal15 16-bit i/o exte rnal address bus (a0 to a15) j port ah pah0 to pah8 9-bit i/o external address bus (a16 to a24) j port dl pdl0 to pdl15 16-bit i/o external data bus (d0 to d15) o port cs pcs0, pcs3, pcs4, pcs7 4-bit i/o external bus interface control signal output j port ct pct0,pct1, pct4, pct5 4-bit i/o external bus interface control signal output j port cm pcm0 to pcm4 5-bit i/o wait insertion signal input internal system clock output external bus interface control signal i/o d, j port cd pcd0 to pcd3 4-bit i/o external bus interface control signal output j, k port bd pbd0, pbd1 2-bit i/o dma controller output j remark the cautions are explained on the following page.
chapter 13 port functions user's manual u14980ej2v1ud 369 cautions 1. when switching the mode of a port that functions as an output or i /o pin to control mode, be sure to follow the procedure below. <1> set the inactive level of the signals output in control mode to the a ppropriate bits in port n (n = 0 to 2, 4, al, ah, dl, cs, ct, cm, cd, and bd). <2> the mode is switched to control mode by the port n mode control register (pmcn). if <1> above is not performed, the contents of port n may be output for a moment when the mode is switched from por t mode to control mode. 2. when port manipulation is pe rformed by a bit manipulation instruction (set1, clr1, or not1), perform a byte-data read of the port, process th e data of only the bits to be manipulated, and write the byte data after conversion back to the port. for example, in ports in whic h input and output are mixed, because the contents of the output latch are overwritten to bi ts other than the bits for manipulati on, the output latch of the input pin becomes undefined (in the input mode, however, th e pin status does not change because the output buffer is off). therefore, when switching the port from input to output, set the expected output value to the corresponding bit, and then switch to the outpu t port. this is the same as when the control mode and output ports are mixed. 3. the state of a port pin can be read by setting the port n mode register (pmn) to the input mode regardless of the settings of th e pmcn register. when the pmn register is set to the output mode, the value of the port n register (pn) can be read in the port mode while the output state of the alternate function can be read in the control mode.
chapter 13 port functions user's manual u14980ej2v1ud 370 (2) function when each port?s pins are reset a nd registers that set the port/control mode port name pin name pin function after reset register that sets the mode p01/intp000/ti000 p01 (input mode) p02/intp001 p02 (input mode) p03/to00 p03 (input mode) pmc0 p04/dmarq0/intp100 p04 (input mode) port 0 p05/dmarq1/intp101 p05 (input mode) pmc0, pfc0 p11/intp010/ti010 p11 (input mode) port 1 p12/intp011 p12 (input mode) pmc1 p20/nmi nmi ? port 2 p24/tc0/intp110 p24 (input mode) pmc2, pfc2 p40/txd0/so0 p40 (input mode) p41/rxd0/si0 p41 (input mode) pmc4, pfc4 p42/sck0 p42 (input mode) pmc4 p43/txd1/so1 p43 (input mode) p44/rxd1/si1 p44 (input mode) pmc4, pfc4 port 4 p45/sck1 p45 (input mode) pmc4 port 7 p70/ani0 to p73/ani3 p70 to p73 (input mode) ? port bd pbd0/dmaak0, pbd1/dmaak1 pbd0, pbd1 (input mode) pmcbd pcm0/wait pcm0 (input mode) wait pcm1/clkout pcm1 (input mode) clkout pcm2/hldak pcm2 (input mode) hldak pcm3/hldrq pcm3 (input mode) hldrq port cm pcm4/refrq pcm4 (input mode) refrq pmccm pct0/lwr/ldqm pct0 (input mode) lwr/ldqm pct1/uwr/udqm pct1 (input mode) uwr/udqm pct4/rd pct4 (input mode) rd port ct pct5/we pct5 (input mode) we pmcct pcs0/cs0 pcs0 (input mode) cs0 pcs3/cs3 pcs3 (input mode) cs3 pcs4/cs4 pcs4 (input mode) cs4 port cs pcs7/cs7 pcs7 (input mode) cs7 pmccs pcd0/sdcke pcd0 (input mode) sdcke pcd1/sdclk pcd1 (input mode) sdclk pmccd pcd2/lbe/sdcas pcd2 (input mode) lbe/sdcas port cd pcd3/ube/sdras pcd3 (input mode) ube/sdras pmccd, pfccd port ah pah0/a16 to pah8/a24 pah0 to pah8 (input mode) a16 to a24 pmcah port al pal0/a0 to pal15/a15 pah0 to pah15 (input mode) a0 to a15 pmcal port dl pdl0/d0 to pdl15/d15 pdl0 to pdl15 (input mode) d0 to d15 pmcdl
chapter 13 port functions user's manual u14980ej2v1ud 371 (3) block diagram of port figure 13-1. block diagram of type a internal bus wr pmc wr pm wr port rd in pmc03 pm03 p03 output signal in control mode selector selector selector p03 address
chapter 13 port functions user's manual u14980ej2v1ud 372 figure 13-2. block diagram of type b wr pmc wr pm wr port rd in pmcmn pmmn pmn selector selector pmn address noise elimination edge detection input signal in control mode internal bus remark m: port number n: bit number figure 13-3. block diagram of type c rd in p7n anin sample & hold circuit input signal in control mode internal bus remark n = 0 to 3
chapter 13 port functions user's manual u14980ej2v1ud 373 figure 13-4. block diagram of type d wr pmc mode0 to mode2 wr port rd in pmccmn wr pm pmcmn pcmn pcmn address input signal in control mode internal bus selector selector remark n = 0, 3 figure 13-5. block diagram of type f rd in p20 address noise elimination edge detection 1 nmi internal bus selector
chapter 13 port functions user's manual u14980ej2v1ud 374 figure 13-6. block diagram of type g wr pmc wr pm rd in pmc4n pm4n wr port p4n p4n address output signal in control mode internal bus selector selector selector selector wr pfc pfc4n remark n = 0, 3
chapter 13 port functions user's manual u14980ej2v1ud 375 figure 13-7. block diagram of type h wr pfc wr pmc wr pm wr port rd in pfcmn pmcmn pmmn pmn pmn address input signal in control mode internal bus selector selector selector edge detection remark m: port number n: bit number
chapter 13 port functions user's manual u14980ej2v1ud 376 figure 13-8. block diagram of type j wr pm wr port rd in pmmn wr pmc pmcmn pmn pmn mode0 to mode2 address output signal in control mode internal bus selector selector selector remark m: port number n: bit number
chapter 13 port functions user's manual u14980ej2v1ud 377 figure 13-9. block diagram of type k wr pfc mode0 to mode2 wr pmc wr pm wr port rd in pfcmn pmcmn pmmn pmn pmn address output signal in control mode internal bus selector selector selector selector remark m: port number n: bit number
chapter 13 port functions user's manual u14980ej2v1ud 378 figure 13-10. block diagram of type m wr pmc wr pm wr port rd in pmc4n pm4n p4n p4n address input signal in control mode output signal in control mode sckx output enable signal internal bus selector selector selector remark n = 2, 5 x: 0 (when n = 2) 1 (when n = 5)
chapter 13 port functions user's manual u14980ej2v1ud 379 figure 13-11. block diagram of type n wr pmc wr pm rd in pmc24 pm24 wr port p24 p24 address output signal in control mode internal bus selector selector selector wr pfc pfc24 input signal in control mode
chapter 13 port functions user's manual u14980ej2v1ud 380 figure 13-12. block diagram of type o wr pm wr port rd in pmdln wr pmc pmcdln pdln pdln address output signal in control mode input signal in control mode input/output control internal bus selector selector selector input/output control mode0 to mode2 remark n = 0 to 15
chapter 13 port functions user's manual u14980ej2v1ud 381 13.3 port pin functions 13.3.1 port 0 port 0 is a 5-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset p0 ? ? p05 p04 p03 p02 p01 ? fffff400h undefined bit position bit name function 5 to 1 p0n (n = 5 to 1) port 0 i/o port in addition to their function as port pins, the port 0 pins can also operate as real-time pulse unit (rpu) inputs/outputs, external interrupt request inpu ts, and dma request inputs in the control mode. (1) operation in control mode port alternate function remark block type p01 intp000/ti000 external interrupt request input/ real-time pulse unit (rpu) input p02 intp001 external interrupt request input b p03 to00 real-time pulse unit (rpu) output a port 0 p04, p05 dmarq0/intp100, dmarq1/intp101 dma request input/ external interrupt request input h (2) i/o mode/control mode setting the port 0 i/o mode setting is performed by means of th e port 0 mode register (pm0), and the control mode setting is performed by means of the port 0 mode contro l register (pmc0) and the port 0 function control register (pfc0). (a) port 0 mode register (pm0) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pm0 1 1 pm05 pm04 pm03 pm02 pm01 1 fffff420h ffh bit position bit name function 5 to 1 pm0n (n = 5 to 1) port mode specifies input/output mode for p0n pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 13 port functions user's manual u14980ej2v1ud 382 (b) port 0 mode control register (pmc0) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmc0 0 0 pmc05 pmc04 pmc03 pmc02 pmc01 0 fffff440h 00h bit position bit name function 5, 4 pmc0n (n = 5, 4) port mode control specifies operation mode of p0n pin in combination with the pfc0 register. 0: i/o port mode 1: external interrupt request (intp101, intp100) input mode/dma request (dmarq1, dmarq0) input mode 3 pmc03 port mode control specifies operation mode of p03 pin. 0: i/o port mode 1: to00 output mode 2 pmc02 port mode control specifies operation mode of p02 pin. 0: i/o port mode 1: external interrupt request (intp001) input mode 1 pmc01 port mode control specifies operation mode of p01 pin. 0: i/o port mode 1: external interrupt request (intp000) input mode/ti000 input mode there is no register that switches between the external interrupt request (intp000) input mode and ti000 input mode ? when ti000 input mode is selected: mask the external interrupt request (intp000) or specify the ccc00 register as compare register. ? when external interrupt request (intp 000) input mode (including timer capture input) is selected: set the eti0 bit of the tmcc01 register to 0.
chapter 13 port functions user's manual u14980ej2v1ud 383 (c) port 0 function control register (pfc0) this register can be read/written in 8- or 1-bit units. bits 7, 6, and 3 to 0, however, are fixed to 0, so writing 1 to these bits is ignored. however, only bits 3 to 0 are fixed to 0 on the in-circuit emulator, and the values written to bits 7 and 6 are reflected. caution when the port mode is specified by the port 0 mode control register (pmc0), the pfc0 setting becomes invalid. 7 6 5 4 3 2 1 0 address after reset pfc0 0 0 pfc05 pfc04 0 0 0 0 fffff460h 00h bit position bit name function 5, 4 pfc0n (n = 5, 4) port function control specifies operation mode of p0n pin in control mode. 0: external interrupt request (intp101, intp100) input mode 1: dma (dmarq1, dmarq0) request input mode
chapter 13 port functions user's manual u14980ej2v1ud 384 13.3.2 port 1 port 1 is a 2-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset p1 ? ? ? ? ? p12 p11 ? fffff402h undefined bit position bit name function 2, 1 p1n (n = 2, 1) port 1 i/o port in addition to their function as port pins, the port 1 pins can also operate as real-time pulse unit (rpu) inputs and external interrupt request inputs in the control mode. (1) operation in control mode port alternate function remark block type p11 ti010/intp010 external interrupt request input/ real-time pulse unit (rpu) input port 1 p12 intp011 external interrupt request input b (2) i/o mode/control mode setting the port 1 i/o mode setting is performed by means of th e port 1 mode register (pm1), and the control mode setting is performed by means of the port 1 mode control register (pmc1). (a) port 1 mode register (pm1) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pm1 1 1 1 1 1 pm12 pm11 1 fffff422h ffh bit position bit name function 2, 1 pm1n (n = 2, 1) port mode specifies input/output mode for p1n pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 13 port functions user's manual u14980ej2v1ud 385 (b) port 1 mode control register (pmc1) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmc1 0 0 0 0 0 pmc12 pmc11 0 fffff442h 00h bit position bit name function 2 pmc12 port mode control specifies operation mode of p12 pin. 0: i/o port mode 1: external interrupt request (intp011) input mode 1 pmc11 port mode control specifies operation mode of p11 pin. 0: i/o port mode 1: external interrupt request (intp010) input mode/ti010 input mode there is no register that switches between the external interrupt request (intp010) input mode and ti010 input mode. ? when the ti010 input mode is selected: mask the external interrupt (intp010) or specify the ccc10 register as compare register. ? when external interrupt request (intp 010) input mode (including timer capture input) is selected: set the eti1 bit of the tmcc11 register to 0.
chapter 13 port functions user's manual u14980ej2v1ud 386 13.3.3 port 2 p20 of port 2 is an input-only port and p24 is an i/o port. caution p20 is fixed to nmi input. the level of th e nmi input can be read regardless of the pm2 and pmc2 registers? value. 7 6 5 4 3 2 1 0 address after reset p2 ? ? ? p24 ? ? ? p20 fffff404h undefined bit position bit name function 4, 0 p2n (n = 4, 0) port 2 i/o port in addition to their function as port pins, the port 2 pins can also operate as the external interrupt request inputs and the dma end (terminal count) sign al outputs in the control mode. (1) operation in control mode port alternate function remark block type p20 nmi non-maskable interrupt request input f port 2 p24 tc0/intp110 dma end signal outputs/external interrupt request inputs n (2) i/o mode/control mode setting the port 2 i/o mode setting is performed by means of th e port 2 mode register (pm2), and the control mode setting is performed by means of the port 2 mode contro l register (pmc2) and the port 2 function control register (pfc2). (a) port 2 mode register (pm2) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pm2 1 1 1 pm24 1 1 1 1 fffff424h ffh bit position bit name function 4 pm24 port mode specifies input/output mode for p24 pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 13 port functions user's manual u14980ej2v1ud 387 (b) port 2 mode control register (pmc2) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmc2 0 0 0 pmc24 0 0 0 1 fffff444h 01h bit position bit name function 4 pmc24 port mode control specifies operation mode of p24 pin in combination with the pfc2 register. 0: i/o port mode 1: external input request (intp110) input mode/ dma end signal (tc0) output mode (c) port 2 function control register (pfc2) this register can be read/written in 8- or 1-bit units. bits 7 to 5 and 3 to 0, however, are fixed to 0 by hardware, so writing 1 to this bit is ignored. howeve r, only bits 3 to 0 are fixed to 0 on the in-circuit emulator, and the values written to bits 7 to 5 are reflected. caution when the port mode is specified by the port 2 mode control register (pmc2), the pfc2 setting becomes invalid. 7 6 5 4 3 2 1 0 address after reset pfc2 0 0 0 pfc24 0 0 0 0 fffff464h 00h bit position bit name function 4 pfc24 port function control specifies operation mode of p24 pin in control mode. 0: external interrupt request (intp110) input mode 1: dma end signal (tc0) output mode
chapter 13 port functions user's manual u14980ej2v1ud 388 13.3.4 port 4 port 4 is a 6-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset p4 ? ? p45 p44 p43 p42 p41 p40 fffff408h undefined bit position bit name function 5 to 0 p4n (n = 5 to 0) port 4 i/o port in addition to their function as port pins, the port 4 pi ns can also operate as the serial interface (uart0/csi0, uart1/csi1) i/o in the control mode. (1) operation in control mode port alternate function remark block type p40 txd0/so0 g p41 rxd0/si0 h p42 sck0 serial interface (uart0/csi0) i/o m p43 txd1/so1 g p44 rxd1/si1 h port 4 p45 sck1 serial interface (uart1/csi1) i/o m (2) i/o mode/control mode setting the port 4 i/o mode setting is performed by means of th e port 4 mode register (pm4), and the control mode setting is performed by means of the port 4 mode contro l register (pmc4) and the port 4 function control register (pfc4). (a) port 4 mode register (pm4) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pm4 1 1 pm45 pm44 pm43 pm42 pm41 pm40 fffff428h ffh bit position bit name function 5 to 0 pm4n (n = 5 to 0) port mode specifies input/output mode for p4n pin 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 13 port functions user's manual u14980ej2v1ud 389 (b) port 4 mode control register (pmc4) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmc4 0 0 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 fffff448h 00h bit position bit name function 5 pmc45 port mode control specifies operation mode of p45 pin. 0: i/o port mode 1: sck1 input/output mode 4 pmc44 port mode control specifies operation mode of p44 pin. 0: i/o port mode 1: rxd1/si1 input mode 3 pmc43 port mode control specifies operation mode of p43 pin. 0: i/o port mode 1: txd1/so1 output mode 2 pmc42 port mode control specifies operation mode of p42 pin. 0: i/o port mode 1: sck0 input/output mode 1 pmc41 port mode control specifies operation mode of p41 pin. 0: i/o port mode 1: rxd0/si0 input mode 0 pmc40 port mode control specifies operation mode of p40 pin. 0: i/o port mode 1: txd0/so0 output mode
chapter 13 port functions user's manual u14980ej2v1ud 390 (c) port 4 function control register (pfc4) this register can be read/written in 8- or 1-bit units. bits 7 to 5 and 2, however, are fixed to 0, so writing 1 to these bits is ignored. caution when the port mode is specified by the port 4 mode control register (pmc4), the pfc4 register setting becomes invalid. 7 6 5 4 3 2 1 0 address after reset pfc4 0 0 0 pfc44 pfc43 0 pfc41 pfc40 fffff468h 00h bit position bit name function 4 pfc44 port function control specifies operation mode of p44 pin in control mode. 0: si1 input mode 1: rxd1 input mode 3 pfc43 port function control specifies operation mode of p43 pin in control mode. 0: so1 output mode 1: txd1 output mode 1 pfc41 port function control specifies operation mode of p41 pin in control mode. 0: si0 input mode 1: rxd0 input mode 0 pfc40 port function control specifies operation mode of p40 pin in control mode. 0: so0 output mode 1: txd0 output mode
chapter 13 port functions user's manual u14980ej2v1ud 391 13.3.5 port 7 port 7 is a 4-bit input-only port whose pins are fixed to input. 7 6 5 4 3 2 1 0 address after reset p7 ? ? ? ? p73 p72 p71 p70 fffff40eh undefined bit position bit name function 3 to 0 p7n (n = 3 to 0) port 7 input-only port in addition to their function as port pins, the port 7 pins can also operate as the analog inputs to the a/d converter in the control mode. (1) operation in control mode port alternate function remark block type port 7 p73 to p70 ani3 to ani0 analog input to a/d converter c caution when performing a/d conversion by selecting a pin from ani0 to ani3, the resolution of the a/d conversion may drop when port 7 (p7) is read during a/d conversion (adcs bit of adm0 register = 1). if a digital pulse is applied to the pin adjacent to the pin executing a/d conversion, the a/d conversion value may not be obt ained as expected due to coupl ing noise. do not apply a digital pulse to the pi n adjacent to the pin executing a/d conversion.
chapter 13 port functions user's manual u14980ej2v1ud 392 13.3.6 port al port al (pal) is a 16-bit i/o port that can be set to the input or output mode in 1-bit units. if the higher 8 bits of port al are used as port alh (pal h) and the lower 8 bits as port all (pall), these 8-bit ports can be set in the input or output mode in 1-bit units. 15 14 13 12 11 10 9 8 address after reset pal pal15 pal14 pal13 pal12 pal11 pal10 pal9 pal8 fffff001h undefined 7 6 5 4 3 2 1 0 address pal7 pal6 pal5 pal4 pal3 pal2 pal1 pal0 fffff000h bit position bit name function 15 to 0 paln (n = 15 to 0) port al i/o port in addition to their functions as port pins, in the control mode, the port al pins operate as an address bus for when the memory is externally expanded. (1) operation in control mode port alternate function remark block type port al pal15 to pal0 a15 to a0 address bus when memory expanded j
chapter 13 port functions user's manual u14980ej2v1ud 393 (2) i/o mode/control mode setting the port al i/o mode setting is performed by means of the port al mode register (pmal), and control mode setting is performed by means of the port al mode control register (pmcal). (a) port al mode register (pmal) the port al mode register (pmal) c an be read/written in 16-bit units. if the higher 8 bits of pmal are used as a port al mode register h (pmalh), and the lower 8 bits as a port al mode register l (pmall), these two 8-bit port mode registers can be read/written in 8- or 1-bit units. 15 14 13 12 11 10 9 8 address after reset pmal pmal15 pmal14 pmal13 pmal12 pma l11 pmal10 pmal9 pmal8 fffff021h ffffh 7 6 5 4 3 2 1 0 address pmal7 pmal6 pmal5 pmal4 pmal3 pmal2 pmal1 pmal0 fffff020h bit position bit name function 15 to 0 pmaln (n = 15 to 0) port mode specifies input/output mode for paln pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port al mode control register (pmcal) the port al mode control register (pmcal ) can be read/written in 16-bit units. if the higher 8 bits of pmcal are used as a port al mode control register h (pmcalh), and the lower 8 bits as a port al mode control register l (p mcall), these two 8-bit port mode registers can be read/written in 8- or 1-bit units. 15 14 13 12 11 10 9 8 address after reset pmcal pmcal15 pmcal14 pmcal13 pmcal12 pmcal11 pmcal10 pmcal9 pmcal8 fffff041h ffffh 7 6 5 4 3 2 1 0 address pmcal7 pmcal6 pmcal5 pmcal4 pmcal3 pmcal2 pmcal1 pmcal0 fffff040h bit position bit name function 15 to 0 pmcaln (n = 15 to 0) port mode control specifies operation mode of paln pin. 0: i/o port mode 1: a15 to a0 output mode
chapter 13 port functions user's manual u14980ej2v1ud 394 13.3.7 port ah port ah (pah) is a 16-bit i/o port that can be se t in the input or output mode in 1-bit units. if the higher 8 bits of port ah are used as port ahh ( pahh) and the lower 8 bits as port ahl (pahl), these 8-bit ports can be set in the input or output mode in 1-bit units. bits 15 to 9 of port ah (bits 7 to 1 of port ahh) are undefined. 15 14 13 12 11 10 9 8 address after reset pah ? ? ? ? ? ? ? pah8 fffff003h undefined 7 6 5 4 3 2 1 0 address pah7 pah6 pah5 pah4 pah3 pah2 pah1 pah0 fffff002h bit position bit name function 8 to 0 pahn (n = 8 to 0) port ah i/o port in addition to their functions as port pins, in the control mode, the port ah pins operate as an address bus for when the memory is externally expanded. (1) operation in control mode port alternate function pin name remark block type port ah pal8 to pal0 a24 to a16 address bus when memory expanded j
chapter 13 port functions user's manual u14980ej2v1ud 395 (2) i/o mode/control mode setting the port ah i/o mode setting is performed by means of the port ah mode register (pmah), and the control mode setting is performed by means of the po rt ah mode control register (pmcah). (a) port ah mode register (pmah) the port ah mode register (pmah) c an be read/written in 16-bit units. if the higher 8 bits of pmah are used as a port ah mode register h (pmahh), and the lower 8 bits as a port ah mode register l (pmahl), these two 8-bit po rt mode registers can be read/written in 8- or 1-bit units. bits 15 to 9 of pmah (bits 7 to 1 of pmahh) are fixed to 1. 15 14 13 12 11 10 9 8 address after reset pmah 1 1 1 1 1 1 1 pmah8 fffff023h ffffh 7 6 5 4 3 2 1 0 address pmah7 pmah6 pmah5 pmah4 pmah3 pmah2 pmah1 pmah0 fffff022h bit position bit name function 8 to 0 pmahn (n = 8 to 0) port mode specifies input/output mode for pahn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port ah mode control register (pmcah) the port ah mode control register (pmcah ) can be read/written in 16-bit units. if the higher 8 bits of pmcah are used as a port ah mode control register h (pmcahh), and the lower 8 bits as a port ah mode control register l (pmc ahl), these two 8-bit port mode registers can be read/written in 8- or 1-bit units. bits 15 to 9 of pmcah (bits 7 to 1 of pmcahh) are fixed to 0. 15 14 13 12 11 10 9 8 address after reset pmcah 0 0 0 0 0 0 0 pmcah8 fffff043h 01ffh 7 6 5 4 3 2 1 0 address pmcah7 pmcah6 pmcah5 pmcah4 pm cah3 pmcah2 pmcah1 pmcah0 fffff042h bit position bit name function 8 to 0 pmcahn (n = 8 to 0) port mode control specifies operation mode of pahn pin. 0: i/o port mode 1: a24 to a16 output mode
chapter 13 port functions user's manual u14980ej2v1ud 396 13.3.8 port dl port dl (pdl) is a 16-bit i/o port that can be se t in the input or output mode in 1-bit units. if the higher 8 bits of port dl are used as port dlh (pdl h), and the lower 8 bits as port dll (pdll), these 8-bit ports can be set in the input or output mode in 1-bit units. 15 14 13 12 11 10 9 8 address after reset pdl pdl15 pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 fffff005h undefined 7 6 5 4 3 2 1 0 address pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 fffff004h bit position bit name function 15 to 0 pdln (n = 15 to 0) port dl i/o port in addition to their functions as port pins, in the control mode, the port dl pins operate as a data bus for when the memory is externally expanded. (1) operation in control mode port alternate function pin name remark block type port dl pdl15 to pdl0 d15 to d0 data bus when memory expanded o (2) i/o mode/control mode setting the port dl i/o mode setting is performed by means of the port dl mode register (pmdl), and the control mode setting is performed by means of the po rt dl mode control register (pmcdl). (a) port dl mode register (pmdl) the port dl mode register (pmdl) can be read/written in 16-bit units. if the higher 8 bits of pmdl are used as a port dl mode register h (pmdlh), and the lower 8 bits as a port dl mode register l (pmdll), these two 8-bit por t mode registers can be read/written in 8- or 1-bit units. 15 14 13 12 11 10 9 8 address after reset pmdl pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 fffff025h ffffh 7 6 5 4 3 2 1 0 address pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 fffff024h bit position bit name function 15 to 0 pmdln (n = 15 to 0) port mode specifies input/output mode for pdln pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 13 port functions user's manual u14980ej2v1ud 397 (b) port dl mode control register (pmcdl) the port dl mode control register (pmcdl ) can be read/written in 16-bit units. if the higher 8 bits of pmcdl are used as a port dl mo de control register h (pmcdlh), and the lower 8 bits as a port dl mode control register l (pmcdll), these tw o 8-bit port mode registers can be read/written in 8- or 1-bit units. 15 14 13 12 11 10 9 8 address after reset pmcdl pmcdl15 pmcdl14 pmcdl13 pmcdl12 pmcdl11 pmcdl10 pmcdl9 pmcdl8 fffff045h ffffh 7 6 5 4 3 2 1 0 address pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 fffff044h bit position bit name function 15 to 0 pmcdln (n = 15 to 0) port mode control specifies operation mode of pdln pin. 0: i/o port mode 1: d15 to d0 output mode caution the d8 to d15 pins are in the input status in romless mode 1.
chapter 13 port functions user's manual u14980ej2v1ud 398 13.3.9 port cs port cs is a 4-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset pcs pcs7 ? ? pcs4 pcs3 ? ? pcs0 fffff008h undefined bit position bit name function 7, 4, 3, 0 pcsn (n = 7, 4, 3, 0) port cs i/o port in addition to their function as port pins, in the control mo de, the port pins can also operate as the chip select signal outputs when externally expanding memory. (1) operation in control mode port alternate function pin name remark block type port cs pcs0, pcs3, pcs4, pcs7 cs0, cs3, cs4, cs7 chip select signal output j (2) i/o mode/control mode setting the port cs i/o mode setting is performed by means of the port cs mode register (pmcs), and the control mode setting is performed by means of the po rt cs mode control register (pmccs). (a) port cs mode register (pmcs) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmcs pmcs7 1 1 pmcs4 pmcs3 1 1 pmcs0 fffff028h ffh bit position bit name function 7, 4, 3, 0 pmcsn (n = 7, 4, 3, 0) port mode specifies input/output mode for pcsn pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 13 port functions user's manual u14980ej2v1ud 399 (b) port cs mode control register (pmccs) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmccs pmccs7 0 0 pmccs4 pmccs3 0 0 pmccs0 fffff048h 99h bit position bit name function 7, 4, 3, 0 pmccsn (n = 7, 4, 3, 0) port mode control specifies operation mode of pcsn pin. 0: i/o port mode 1: csn output mode
chapter 13 port functions user's manual u14980ej2v1ud 400 13.3.10 port ct port ct is a 4-bit i/o port that can be set to input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset pct ? ? pct5 pct4 ? ? pct1 pct0 fffff00ah undefined bit position bit name function 5, 4,1,0 pctn (n = 5, 4,1,0) port ct i/o port in addition to their function as port pins, in the control mo de, the port ct pins operate as control signal outputs for when the memory is externally expanded. (1) operation in control mode port alternate function pin name remark block type pct0 lwr/ldqm write strobe signal output/ output disable/write mask signal pct1 uwr/udqm write strobe signal output/ output disable/write mask signal pct4 rd read strobe signal output port ct pct5 we write enable signal output j (2) i/o mode/control mode setting the port ct i/o mode setting is performed by means of the port ct mode regist er (pmct), and the control mode setting is performed by means of the po rt ct mode control register (pmcct). (a) port ct mode register (pmct) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmct 1 1 pmct5 pmct4 1 1 pmct1 pmct0 fffff02ah ffh bit position bit name function 5, 4, 1, 0 pmctn (n = 5, 4, 1, 0) port mode specifies input/output mode for pctn pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 13 port functions user's manual u14980ej2v1ud 401 (b) port ct mode control register (pmcct) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmcct 0 0 pmcct5 pmcct4 0 0 pmcct1 pmcct0 fffff04ah 33h bit position bit name function 5 pmcct5 port mode control specifies operation mode of pct5 pin. 0: i/o port mode 1: we output mode 4 pmcct4 port mode control specifies operation mode of pct4 pin. 0: i/o port mode 1: rd output mode 1 pmcct1 port mode control specifies operation mode of pct1 pin. 0: i/o port mode 1: uwr/udqm output mode (uwr/udqm signal automatically switched by accessing the targeted me mory of each signal.) 0 pmcct0 port mode control specifies operation mode of pct0 pin. 0: i/o port mode 1: lwr/ldqm output mode (lwr/ldqm signal automatically switched by accessing the targeted me mory of each signal.)
chapter 13 port functions user's manual u14980ej2v1ud 402 13.3.11 port cm port cm is a 5-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset pcm ? ? ? pcm4 pcm3 pcm2 pcm1 pcm0 fffff00ch undefined bit position bit name function 4 to 0 pcmn (n = 4 to 0) port cm i/o port in addition to their function as port pins, in the control mode , the port cm pins operate as the wait insertion signal input, internal system clock output, bus hold control si gnal output, and refresh request signal output from dram. (1) operation in control mode port alternate function pin name remark block type pcm0 wait wait insertion signal input d pcm1 clkout internal system clock output j pcm2 hldak bus hold acknowledge signal output j pcm3 hldrq bus hold request signal input d port cm pcm4 refrq refresh request signal output j (2) i/o mode/control mode setting the port cm i/o mode setting is performed by means of the port cm mode register (pmcm), and the control mode setting is performed by means of the port cm mode control register (pmccm). (a) port cm mode register (pmcm) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmcm 1 1 1 pmcm4 pmcm3 pmcm2 pmcm1 pmcm0 fffff02ch ffh bit position bit name function 4 to 0 pmcmn (n = 4 to 0) port mode specifies input/output mode for pcmn pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 13 port functions user's manual u14980ej2v1ud 403 (b) port cm mode control register (pmccm) this register can be read/written in 8- or 1-bit units. caution if the mode of the pcm1 /clkout pin is change d from the i/o port mode to the clkout mode, a glitch may be generated on the clko ut output immediately after the change. therefore, pull up the clkout pin when using it . in the pll mode (cksel = 0), change the mode to the clkout output mode at a mu ltiple of 1 (ckdiv2 to ckdiv0 bits of ckc register = 000b). 7 6 5 4 3 2 1 0 address after reset pmccm 0 0 0 pmccm4 pmccm3 pmccm2 pmccm1 pmccm0 fffff04ch 1fh bit position bit name function 4 pmccm4 port mode control specifies operation mode of pcm4 pin. 0: i/o port mode 1: refrq output mode 3 pmccm3 port mode control specifies operation mode of pcm3 pin. 0: i/o port mode 1: hldrq input mode 2 pmccm2 port mode control specifies operation mode of pcm2 pin. 0: i/o port mode 1: hldak output mode 1 pmccm1 port mode control specifies operation mode of pcm1 pin. 0: i/o port mode 1: clkout output mode 0 pmccm0 port mode control specifies operation mode of pcm0 pin. 0: i/o port mode 1: wait input mode
chapter 13 port functions user's manual u14980ej2v1ud 404 13.3.12 port cd port cd is a 4-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset pcd ? ? ? ? pcd3 pcd2 pcd1 pcd0 fffff00eh undefined bit position bit name function 3 to 0 pcdn (n = 3 to 0) port cd i/o port in addition to their function as port pins, the port cd pi ns operate as the clock enable signal output to sdram, synchronous clock output, column address strobe signal output, row address strobe signal output, and byte enable signal output to sdram upon byte access, in the control mode. (1) operation in control mode port alternate function pin name remark block type pcd0 sdcke clock enable signal output pcd1 sdclk synchronous clock output j pcd2 lbe/sdcas byte enable signal output/ column address strobe signal output port cd pcd3 ube/sdras byte enable signal output/ row address strobe signal output k (2) i/o mode/control mode setting the port cd i/o mode setting is performed by means of the port cd mode register (pmcd), and the control mode setting is performed by means of the port cd mode control register (pmccd) and the port cd function control register (pfccd). (a) port cd mode register (pmcd) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmcd 1 1 1 1 pmcd3 pmcd2 pmcd1 pmcd0 fffff02eh ffh bit position bit name function 3 to 0 pmcdn (n = 3 to 0) port mode specifies input/output mode for pcdn pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 13 port functions user's manual u14980ej2v1ud 405 (b) port cd mode control register (pmccd) this register can be read/written in 8- or 1-bit units. cautions 1. do not perform the sdclk and s dcke output mode setting simultaneously. be sure to perform the sdclk output mode setting before the sdcke output mode setting. 2. bits 1 and 0 of the pmccd register become sdclk output mode and sdcke output mode after the reset is released, however, bits 3 and 2 become ube output mode and lbe output mode. when using sdram be sure to set the sdras output mode and sdcas output mode using the pfccd register. 7 6 5 4 3 2 1 0 address after reset pmccd 0 0 0 0 pmccd3 pmccd2 pmccd1 pmccd0 fffff04eh 0fh bit position bit name function 3 pmccd3 port mode control specifies operation mode of pcd3 pin. 0: i/o port mode 1: ube/sdras output mode 2 pmccd2 port mode control specifies operation mode of pcd2 pin. 0: i/o port mode 1: lbe/sdcas output mode 1 pmccd1 port mode control specifies operation mode of pcd1 pin. 0: i/o port mode 1: sdclk output mode 0 pmccd0 port mode control specifies operation mode of pcd0 pin. 0: i/o port mode 1: sdcke output mode
chapter 13 port functions user's manual u14980ej2v1ud 406 (c) port cd function control register (pfccd) this register can be read/written in 8- or 1-bit units. bits 7 to 4, 1, and 0, however, are fixed to 0, so writing 1 to these bits is ignored. caution when the port mode is specified by the port cd mode control register (pmccd), the pfccd setting becomes invalid. 7 6 5 4 3 2 1 0 address after reset pfccd 0 0 0 0 pfccd3 pfccd2 0 0 fffff04fh 00h bit position bit name function 3 pfccd3 port function control specifies operation mode of pcd3 pin in control mode. 0: ube output mode 1: sdras output mode 2 pfccd2 port function control specifies operation mode of pcd2 pin in control mode. 0: lbe output mode 1: sdcas output mode
chapter 13 port functions user's manual u14980ej2v1ud 407 13.3.13 port bd port bd is a 2-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset pbd ? ? ? ? ? ? pbd1 pbd0 fffff012h undefined bit position bit name function 1, 0 pbdn (n = 1, 0) port bd i/o port in addition to their function as port pins, the port bd pins operate as the dma acknowledge signal outputs in the control mode. (1) operation in control mode port alternate function pin name remark block type port bd pbd0, pbd1 dmaak0, dmaak1 dma acknowledge signal output j (2) i/o mode/control mode setting the port bd i/o mode setting is performed by means of the port bd mode register (pmbd), and the control mode setting is performed by means of the po rt bd mode control register (pmcbd). (a) port bd mode register (pmbd) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmbd 1 1 1 1 1 1 pmbd1 pmbd0 fffff032h ffh bit position bit name function 1, 0 pmbdn (n = 1, 0) port mode specifies input/output mode for pbdn pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 13 port functions user's manual u14980ej2v1ud 408 (b) port bd mode control register (pmcbd) this register can be read/written in 8- or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmcbd 0 0 0 0 0 0 pmcbd1 pmcbd0 fffff052h 00h bit position bit name function 1, 0 pmcbdn (n = 1, 0) port mode control specifies operation mode of pbdn pin. 0: i/o port mode 1: dmaakn output mode
user's manual u14980ej2v1ud 409 chapter 14 reset functions when a low-level signal is input to the reset pin, a system reset is effected and the hardware is initialized. when the reset signal level changes from low to high, the reset state is rel eased and cpu starts program execution. register contents must be in itialized as required in the program. 14.1 features the reset pin (reset) incorporates a nois e eliminator that uses analog delay (= 60 ns) to prevent malfunction due to noise. 14.2 pin functions during a system reset, most pins (all but the clkout, reset, x2, v dd , v ss , cv dd , cv ss av dd , av ref , and av ss pins) enter the high impedance state. therefore, when memory is connect ed externally, a pull-up or pull-down resistor must be connected to the specified pins of ports al, ah, dl, cs, ct, cm, cd, and bd. if no resistor is connected there, external memory may be destroyed when these pins enter the high impedance state. for the same reason, the output pins of the internal peripheral i/o functi ons and other output ports should be handled in the same manner. the operation status of eac h pin during reset is shown below (table 14-1). table 14-1. operation status of each pin during reset pin name pin state a0 to a15, a16 to a24, d0 to d15, cs0, cs3, cs4, cs7, lwr, uwr, ldqm, udqm, rd, we, wait, hldak, hldrq, refreq, sdcke, sdclk, lbe, ube, sdcas, sdras high impedance clkout operating ports 0 to 2, 4, 7, bd (input) port pin ports al, ah, dl, cm, ct, cs, cd (control mode) . .
chapter 14 reset functions user's manual u14980ej2v1ud 410 (1) receiving the reset signal reset (input) internal system reset signal eliminate noise ?? reset acknowledgement reset release analog delay analog delay analog delay note note the internal system reset signal continues in the active state for at least 4 system clock cycles after reset is cleared by the reset signal. (2) reset when turning on the power in a reset operation when the power is turned on, because of the low-level width of the reset signal, it is necessary to secure the oscillation stabilization time between when the power is turned on and when the reset is acknowledged. reset (input) v dd ? reset release analog delay oscillation stabilization time
chapter 14 reset functions user's manual u14980ej2v1ud 411 14.3 initialization initialize the contents of each regist er as necessary while programming. the initial values of the cpu, inte rnal ram, and on-chip peripheral i/o afte r a reset are shown in table 14-2. table 14-2. initial value of cpu, internal ram, and on-chip periphera l i/o after reset (1/3) internal hardware register name initial value after reset general-purpose register (r0) 00000000h general-purpose registers (r1 to r31) undefined program registers program counter (pc) 00000000h status saving registers during in terrupt (eipc, eipsw) undefined status saving registers during nmi (fepc, fepsw) undefined interrupt source register (ecr) 00000000h program status word (psw) 00000020h status saving registers during callt execution (ctpc, ctpsw) undefined status saving registers during exception/debug trap (dbpc, dbpsw) undefined cpu system registers callt base pointer (ctbp) undefined internal ram ? undefined ports (p0 to p2, p4, p7, pal, pah, pdl, pcs, pct, pcm, pcd, pbd) undefined mode registers (pm0 to pm2, pm4, pmcs, pmct, pmcm, pmcd, pmbd) ffh mode registers (pmal, pmah, pmdl) ffffh mode control registers (pmc0, pmc1, pmc4, pmcbd) 00h mode control register (pmc2) 01h mode control registers (pmcal, pmcdl) ffffh mode control register (pmcah) 01ffh mode control register (pmccs) 99h mode control register (pmcct) 33h mode control register (pmccm) 1fh mode control register (pmccd) 0fh port functions function control registers (pfc0, pfc2, pfc4, pfccd) 00h timer cn (tmcn) (n = 0, 1) 0000h capture/compare registers cn0 and cn1 (cccn0, cccn1) (n = 0, 1) 0000h timer mode control register cn0 (tmccn0) (n = 0, 1) 00h timer mode control register cn1 (tmccn1) (n = 0, 1) 20h timer dn (tmdn) (n = 0 to 3) 0000h compare register (cmdn) (n = 0 to 3) 0000h on-chip peripher al i/o timer/counter functions timer mode control register dn (n = 0 to 3) 00h
chapter 14 reset functions user's manual u14980ej2v1ud 412 table 14-2. initial value of cpu, internal ram, and on-chip periphera l i/o after reset (2/3) internal hardware register name initial value after reset clocked serial interface mode regi ster n (csimn) (n = 0, 1) 00h clocked serial interface clock select register n (csicn) (n = 0, 1) 00h clocked serial interface transmit buffer register n (sotbn) (n = 0, 1) 00h serial i/o shift register n (sion) (n = 0, 1) 00h receive-only serial i/o shift regi ster n (sioen) (n = 0, 1) 00h receive buffer register n (rxbn) (n = 0, 1) ffh transmit buffer register n (txbn) (n = 0, 1) ffh asynchronous serial interface mode register n (asimn) (n = 0, 1) 01h asynchronous serial interface status register n (asisn) (n = 0, 1) 00h asynchronous serial interface tran smit status register n (asifn) (n = 0, 1) 00h clock selection register n (cksrn) (n = 0, 1) 00h serial interface functions baud rate generator control register n (brgcn) (n = 0, 1) ffh a/d converter mode registers 0 and 2 (adm0, adm2) 00h a/d converter mode register 1 (adm1) 07h a/d conversion result register n (adcrn) (10 bits) (n = 0 to 3) 0000h a/d converter a/d conversion result register nh (adcrnh) (8 bits) (n = 0 to 3) 00h in-service priority register (ispr) 00h external interrupt mode register n (intmn) (n = 0 to 2) 00h interrupt mask register n (imrn) (n = 0 to 3) ffffh valid edge selection register cn (sescn) (n = 0, 1) 00h interrupt/exception control functions interrupt control registers (ovic00, ovic01, p00ic0, p00ic1, p01ic0, p01ic1, p10ic0, p10ic1, p11ic0, cmicd0 to cmicd3, dmaic0 to dmaic3, csiic0, csiic1, seic0, seic1, sric0, sric1, stic0, stic1, adic) 47h page rom configuration register (prc) 7000h sdram configuration register n (scrn) (n = 3, 4) 0000h memory control functions sdram refresh control register n (rfsn) (n = 3, 4) 0000h dma addressing control register n (dadcn) (n = 0 to 3) 0000h dma byte count register n (dbcn) (n = 0 to 3) undefined dma channel control register n (dchcn) (n = 0 to 3) 00h dma destination address register nh (ddanh) (n = 0 to 3) undefined dma destination address register nl (ddanl) (n = 0 to 3) undefined dma disable status register (ddis) 00h dma restart register (drst) 00h dma source address register nh (dsanh) (n = 0 to 3) undefined dma source address register nl (dsanl) (n = 0 to 3) undefined dma terminal count output control register (dtoc) 01h on-chip peripher al i/o dma functions dma trigger source register n (dtfrn) (n = 0 to 3) 00h
chapter 14 reset functions user's manual u14980ej2v1ud 413 table 14-2. initial value of cpu, internal ram, and on-chip periphera l i/o after reset (3/3) internal hardware register name initial value after reset address setup wait control register (asc) ffffh bus cycle control register (bcc) ffffh bus cycle type configuration regi ster n (bctn) (n = 0, 1) 8888h endian configuration register (bec) 0000h bus size configuration register (bsc) 0000h/5555h chip area selection control register n (cscn) (n = 0, 1) 2c11h bus control functions data wait control register n (dwcn) (n = 0, 1) 7777h command register (prcmd) undefined power save control register (psc) 00h clock control register (ckc) 00h power save control functions power save mode register (psmr) 00h peripheral command register (phcmd) undefined peripheral status register (phs) 00h system wait control register (vswc) 77h on-chip peripher al i/o system control lock register (lockr) 0 h caution ?undefined? in the above table is undefined afte r power-on reset, or undefined as a result of data destruction when reset is input and the data writin g timing has been synchronized. for other reset signals, data is held in the same state it was in before the reset operation.
user's manual u14980ej2v1ud 414 chapter 15 electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v dd pin ? 0.5 to +4.6 v cv dd cv dd pin ? 0.5 to +4.6 v cv ss cv ss pin ? 0.5 to +0.5 v av dd av dd pin ? 0.5 to +4.6 v power supply voltage av ss av ss pin ? 0.5 to +0.5 v input voltage v i except x1 pin, v i < v dd + 3.0 v ? 0.5 to v dd + 0.5 v clock input voltage v k x1, v dd = 3.3 v 0.3 v ? 0.5 to v dd + 1.0 v per pin 4.0 ma output current, low i ol total of all pins 100 ma per pin ? 4.0 ma output current, high i oh total of all pins ? 100 ma output voltage v o v dd = 3.3 v 0.3 v ? 0.5 to v dd + 0.5 v analog input voltage v wasn ani0 to ani3, v dd = 3.3 v 0.3 v, av dd < v dd + 0.5 v ? 0.3 to av dd + 0.3 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 60 to +150 c cautions 1. avoid direct connections among the ic device output (or i/o) pins and between v dd or v cc and gnd. however, direct connections among open-drain and open-c ollector pins are possible, as are direct connecti ons to external circuits that have timing designed to prevent output conflict with pins that become high-impedance. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximu m ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that th e absolute maximum ratings are not exceeded. the ratings and conditions shown below for dc characteristics and ac characteristics are within the range for normal operation and quality assurance. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v. 15 pf operating conditions operation mode inter nal operation clock frequency (f xx ) operating ambient temperature (t a ) power supply voltage (v dd ) direct mode 4 to 20 mhz ? 40 to +85 c v dd = 3.3 v 0.3 v pll mode note 4 to 40 mhz ? 40 to +85 c v dd = 3.3 v 0.3 v note set the input clock frequency (f x ) used in the pll mode to 4.0 to 6.6 mhz. however, when inputting a frequency higher than 4.0 mhz, be sure to set the ckdiv2 to ckdiv0 bits of the clock control register (ckc) to other than 111 (10 f x ).
chapter 15 electrical specifications user's manual u14980ej2v1ud 415 recommended oscillator (a) ceramic resonator (i) kyocera corporation (t a = ?20 to +80 c) x1 x2 c1 c2 r d recommended circuit constant oscillation voltage range type product oscillation frequency f x (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) pbrc4.00hr 4.0 on-chip on-chip 0 3.0 3.6 0.34 pbrc5.00hr note 5.0 on-chip on-chip 0 3.0 3.6 0.27 surface mount pbrc6.00hr note 6.0 on-chip on-chip 0 3.0 3.6 0.33 kbr-4.0mkc 4.0 on-chip on-chip 0 3.0 3.6 0.34 kbr-5.0mkc note 5.0 on-chip on-chip 0 3.0 3.6 0.27 lead kbr-6.0mkc note 6.0 on-chip on-chip 0 3.0 3.6 0.33 note use with a setting other than 10 multiplication. cautions 1. connect the oscillator as clo se to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd703108 and the resonator. 4. the oscillator constant is a reference value based on evalua tion in specific environments by the resonator manufacturer. if the oscillato r characteristics need to be optimized in the actual application, request the res onator manufacturer for evaluation on the implementation circuit. note that the oscilla tion voltage and oscillation frequency merely indicate the characteristi cs of the oscillator. use the in ternal operation conditions of the pd703108 within the specifications of the dc and ac characteristics. (b) external clock input (t a = ?40 to +85 c) x1 x2 open external clock
chapter 15 electrical specifications user's manual u14980ej2v1ud 416 dc characteristics (t a = ?40 to +85 c, v dd = 3.3 v 0.3 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit except for note 1 2.0 v dd + 0.3 v input voltage, high v ih note 1 0.75v dd v dd + 0.3 v except for note 1 ?0.5 0.8 v input voltage, low v il note 1 ?0.5 0.2v dd v direct mode 0.8v dd v dd + 0.3 v clock input voltage, high v xh x1 pin pll mode 0.8v dd v dd + 0.3 v direct mode ?0.5 0.15v dd v clock input voltage, low v xl x1 pin pll mode ?0.5 0.15v dd v v t + note 1 , rising edge 2.0 v schmitt-triggered input threshold voltage v t ? note 1 , falling edge 1.0 v schmitt-triggered input hysteresis width v t + ? v t ? note 1 0.3 v i oh = ?2.5 ma 0.8v dd v output voltage, high v oh i oh = ?100 a v dd ? 0.4 v output voltage, low v ol i ol = 2.5 ma 0.45 v input leakage current, high i lih v i = v dd , except for note 2 10 a input leakage current, low i lil v i = 0 v, except for note 2 ? 10 a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ? 10 a analog pin input leakage current i lwasn note 2 10 a direct mode 2.4 f xx + 30 3.6 f xx + 45 ma during normal operation i dd1 pll mode 2.4 f xx + 30 3.6 f xx + 45 ma direct mode 1.2 f xx + 20 1.8 f xx + 30 ma in halt mode i dd2 pll mode 1.2 f xx + 20 1.8 f xx + 30 ma direct mode 10 30 ma in idle mode i dd3 pll mode 10 30 ma power supply current in stop mode i dd4 10 200 a notes 1. p01/ti000/intp000, p02/intp001, p04/dmarq0/in tp100, p05/dmarq1/intp101, p11/ti010/intp010, p12/intp011, p24/tc0/intp110, p41/rxd0/si0, p 42/sck0, p44/rxd1/si1, p45/sck1, mode0 to mode2, reset 2. p70/ani0 to p73/ani3 remarks 1. typ. values are reference values for when t a = 25 c, v dd = 3.3 v. the current does not include the current flowing through pull-up resistors. 2. f xx : cpu operation frequency
chapter 15 electrical specifications user's manual u14980ej2v1ud 417 data retention characteristics (t a = ?40 to + 85 c) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode and v dd = v dddr 1.5 3.6 v data retention current i dddr v dd = v dddr 10 200 a power supply voltage rise time t rvd 200 s power supply voltage fall time t fvd 200 s power supply voltage hold time (from stop mode setting) t hvd 0 ms stop release signal input time t drel 0 ns data retention high-level input voltage v ihdr note 0.8v dddr v dddr v data retention low-level input voltage v ildr note ? 0.5 0.2v dddr v note p01/ti000/intp000, p02/intp001, p04/dmarq0/in tp100, p05/dmarq1/intp101, p11/ti010/intp010, p12/intp011, p24/tc0/intp110, p41/rxd0/si0, p42/sc k0, p44/rxd1/si1, p45/sck1, mode0 to mode2, reset remark typ. values are reference values for when t a = 25 c. t hvd v dddr t drel v ihdr v ihdr v ildr t fvd t rvd v dd nmi (input) nmi (input) stop mode setup reset (input) (released at falling edge) (released at rising edge)
chapter 15 electrical specifications user's manual u14980ej2v1ud 418 ac characteristics (t a = ?40 to + 85 c, v dd = 3.3 v 0.3 v, v ss = 0 v, output pin load capacitance: c l = 50 pf) ac test input points (a) p01/ti000/intp000, p02/intp001, p04/dmarq0/in tp100, p05/dmarq1/intp101, p11/ti010/intp010, p12/intp011, p24/tc0/intp110, p41/rxd0/si0, p42/s ck0, p44/rxd1/si1, p45/sck1, mode0 to mode2, reset v dd 0.75v input signal dd 0.2v dd 0.75v dd 0.2v dd 0 v test points (b) other than (a) above 2.0 v 0.8 v 2.0 v 0.8 v v dd input signal 0 v test points ac test output test points 0.7v dd 0.2v dd 0.7v dd 0.2v dd output signal test points load condition c l = 50 pf dut (device under test) caution in cases where the load cap acitance is greater than 50 pf due to the circuit configuration, insert a buffer or other elemen t to reduce the devi ce?s load capacitance to 50 pf or lower.
chapter 15 electrical specifications user's manual u14980ej2v1ud 419 (1) clock timing (1/2) parameter symbol conditions min. max. unit direct mode 25 125 ns 10 250 250 ns x1 input cycle <1> t cyx pll mode other than 10 150 250 ns direct mode 5 ns x1 input high-level width <2> t wxh pll mode 50 ns direct mode 5 ns x1 input low-level width <3> t wxl pll mode 50 ns direct mode 4 ns x1 input rise time <4> t xr pll mode 10 ns direct mode 4 ns x1 input fall time <5> t xf pll mode 10 ns clkout output cycle <6> t cyk1 25 250 ns clkout high-level width <7> t wkh1 0.5t ? 5 ns clkout low-level width <8> t wkl1 0.5t ? 6 ns clkout rise time <9> t kr1 5 ns clkout fall time <10> t kf1 4 ns delay time from x1 to clkout <11> t dkx 40 ns delay time from x1 to sdclk <12> t dsx 40 ns sdclk output cycle <13> t cyk2 25 250 ns sdclk high-level width <14> t wkh2 0.5t ? 5 ns sdclk low-level width <15> t wkl2 0.5t ? 6 ns sdclk rise time <16> t kr2 5 ns sdclk fall time <17> t kf2 4 ns remarks 1. t = t cyk1 2. the phase difference between clko ut and sdclk cannot be defined.
chapter 15 electrical specifications user's manual u14980ej2v1ud 420 (1) clock timing (2/2) x1 <2> <1> <3> <5> <4> x1 (direct mode) (pll mode) <5> <1> <2> <3> <4> <11> <11> <12> clkout (output) <8> <9> <7> <10> <6> sdclk (output) <15> <16> <14> <17> <13> (2) output waveform (other than x1 and clkout) parameter symbol conditions min. max. unit output rise time <20> t or 5 ns output fall time <21> t of 4 ns <21> <20> signals other than x1 and clkout
chapter 15 electrical specifications user's manual u14980ej2v1ud 421 (3) reset timing parameter symbol conditions min. max. unit reset pin high-level width <22> t wrsh 500 ns at power-on and at stop mode release 500 + t os ns reset pin low-level width <23> t wrsl except at power-on and at stop mode release 500 ns remark t os : oscillation stabilization time caution thoroughly evaluate the oscillation stabilization time. <22> <23> reset (input)
chapter 15 electrical specifications user's manual u14980ej2v1ud 422 (4) sram, external rom, and external i/o access timing (a) access timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit address, csn output delay time (from clkout ) 2 15 ns address, csn output delay time (from sdclk ) <24> t dka1 0 15 ns address, csn output hold time (from clkout ) 2 13 ns address, csn output hold time (from sdclk ) <25> t hka 0 13 ns rd, iord delay time (from clkout ) 2 13 ns rd, iord delay time (from sdclk ) <26> t dkrdl 0 13 ns rd, iord delay time (from clkout ) 2 13 ns rd, iord delay time (from sdclk ) <27> t hkrdh 0 13 ns uwr, lwr, iowr delay time (from clkout ) 2 13 ns uwr, lwr, iowr delay time (from sdclk ) <28> t dkwrl 0 13 ns uwr, lwr, iowr delay time (from clkout ) 2 13 ns uwr, lwr, iowr delay time (from sdclk ) <29> t hkwrh 0 13 ns wait setup time (to clkout ) 8 ns wait setup time (to sdclk ) <32> t swk 10 ns wait hold time (from clkout ) 2 ns wait hold time (from sdclk ) <33> t hkw 2 ns data input setup time (to clkout ) 8 ns data input setup time (to sdclk ) <34> t skid 10 ns data input hold time (from clkout ) 2 ns data input hold time (from sdclk ) <35> t hkid 2 ns data output delay time (from clkout ) 2 13 ns data output delay time (from sdclk ) <36> t dkod1 0 13 ns data output delay time (from clkout ) 2 15 ns data output delay time (from sdclk ) <37> t dkod2 0 15 ns data float delay time (from clkout ) 2 13 ns data float delay time (from sdclk ) <38> t hkod 0 13 ns remarks 1. maintain at least one of the data input hold times, t hrdid or t hkid . 2. n = 0, 3, 4, 7
chapter 15 electrical specifications user's manual u14980ej2v1ud 423 (a) access timing (sram, external rom, external i/o) (2/2) clkout (output) [when read] [when written] [when written] [when read] rd (output) t1 tw t2 csn (output) <24> <25> <26> <28> <29> <27> <35> <34> <37> <38> <32> <33> <32> <33> a0 to a24 (output) uwr, lwr (output) wait (input) d0 to d15 (i/o) d0 to d15 (i/o) <29> <38> <27> <26> <28> < 36> < 36> sdclk (output) ube, lbe (output) remarks 1. this is the timing when the number of waits based on the dwc0 and dwc1 registers is zero. 2. broken lines indicate high impedance. 3. n = 0, 3, 4, 7
chapter 15 electrical specifications user's manual u14980ej2v1ud 424 (b) read timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit data input setup time (to address) <39> t said (2 + w + w d + w as )t ? 19 ns data input setup time (to rd) <40> t srdid (1.5 + w + w d )t ? 19 ns rd low-level width <41> t wrdl (1.5 + w + w d )t ? 10 ns rd high-level width <42> t wrdh (0.5 + w as + i)t ? 10 ns delay time from address, csn to rd <43> t dard (0.5 + w as )t ? 10 ns delay time from rd to address <44> t drda it ns data input hold time (from rd ) <45> t hrdid 0 ns delay time from rd to data output <46> t drdod (0.5 + i)t ? 10 ns wait setup time (to address) <47> t saw note (1 + w as )t ? 21 ns wait high-level width <50> t wwh t ? 10 ns data output hold time (from uwr, lwr ) <57> t hwrod (0.5 + i)t ? 8 ns note for the first wait sampling when the wait count based on the dwc0 and dwc1 registers is zero. remarks 1. t = t cyk1 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. maintain at least one of the data input hold times t hrdid or t hkid 5. n = 0, 3, 4, 7 6. i: idle state count 7. w as : address setup wait count based on the asc register
chapter 15 electrical specifications user's manual u14980ej2v1ud 425 (b) read timing (sram, external rom, external i/o) (2/2) clkout (output) csn (output) a0 to a24 (output) uwr, lwr rd (output) d0 to d15 (i/o) t1 tw t2 <45> <42> <41> <44> <46> <39> <40> <43> <47> ti tasw <57> <50> wait (input) (output) ube, lbe (output) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait coun t based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0, 3, 4, 7
chapter 15 electrical specifications user's manual u14980ej2v1ud 426 (c) write timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit wait setup time (to address) <47> t saw note (1 + w as )t ? 21 ns wait high-level width <50> t wwh t ? 10 ns delay time from address, csn to uwr, lwr <51> t dawr (0.5 + w as )t ? 10 ns address setup time (to uwr, lwr ) <52> t sawr (1.5 + w + w d + w as )t ? 10 ns delay time from uwr, lwr to address <53> t dwra (0.5 + i)t ? 10 ns uwr, lwr high-level width <54> t wwrh (0.5 + i + w as )t ? 10 ns uwr, lwr low-level width <55> t wwrl (1 + w + w d )t ? 10 ns data output setup time (to uwr, lwr ) <56> t sodwr (0.5 + w + w d )t ? 10 ns data output hold time (from uwr, lwr ) <57> t hwrod (0.5 + i)t ? 8 ns note for the first wait sampling when the wait count based on the dwc0 and dwc1 registers is zero. remarks 1. t = t cyk1 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. n = 0, 3, 4, 7 5. i: idle state count 6. w as : address setup wait count based on the asc register
chapter 15 electrical specifications user's manual u14980ej2v1ud 427 (c) write timing (sram, external rom, external i/o) (2/2) <54> <52> <53> write write <51> <55> <56> csn (output) a0 to a24 (output) uwr, lwr rd (output) <57> clkout (output) t1 tw t2 ti tasw <47> wait (input) <50> (output) d0 to d15 (i/o) read write d0 to d15 (i/o) ube, lbe (output) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait coun t based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0, 3, 4, 7
chapter 15 electrical specifications user's manual u14980ej2v1ud 428 (5) page rom access timing (a) 8-bit bus width (halfword/word acces s), 16-bit bus width (word access) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8 ns wait hold time (from clkout ) <33> t hkw 0 ns data input setup time (to clkout ) <34> t skid 8 ns data input hold time (from clkout ) <35> t hkid 0 ns off-page data input setup time (to address) <39> t said (2 + w + w d + w as )t ? 21 ns off-page data input setup time (to rd) <40> t srdid (1.5 + w + w d )t ? 21 ns data input hold time (from rd ) <45> t hrdid 0 ns delay time from rd to data output <46> t drdod (0.5 + i)t ? 10 ns on-page data input setup time (to address) <64> t soaid (2 + w + w pr + w as )t ? 21 ns remarks 1. t = t cyk1 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. w pr : wait count based on the prc register 5. i: count of idle states insert ed when a write cycle follows a read cycle 6. w as : address setup wait count based on the asc register 7. maintain at least one of the data input hold times t hkid or t hrdid
chapter 15 electrical specifications user's manual u14980ej2v1ud 429 (a) 8-bit bus width (halfword/word acces s), 16-bit bus width (word access) (2/2) csn (output) clkout (output) t1 tdw tw t2 <39> <40> <35> <33> <32> <32> <33> d0 to d15 (i/o) uwr, lwr (output) rd (output) wait (input) <34> to1 tprw tw to2 <64> <34> <35> <45> <33> <32> <33> <32> tasw tasw <46> address (output) note note on-page and off-page addresses are as follows. prc register ma6 ma5 ma4 ma3 on-page address off-page address 0 0 0 0 a0 to a2 a3 to a24 0 0 0 1 a0 to a3 a4 to a24 0 0 1 1 a0 to a4 a5 to a24 0 1 1 1 a0 to a5 a6 to a24 1 1 1 1 a0 to a6 a7 to a24 remarks 1. this is the timing for the following case. wait count based on the dwc0 and dwc1 registers (tdw): 1 wait count based on the prc register (tprw): 1 wait count based on the asc register (tasw): 1 2. broken lines indicate high impedance. 3. n = 0, 3, 4, 7
chapter 15 electrical specifications user's manual u14980ej2v1ud 430 (b) 8-bit bus width (byte access), 16-bit bus width (byte/halfword access) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8 ns wait hold time (from clkout ) <33> t hkw 0 ns data input setup time (to clkout ) <34> t skid 8 ns data input hold time (from clkout ) <35> t hkid 0 ns off-page data input setup time (to address) <39> t said (2 + w + w d + w as )t ? 21 ns off-page data input setup time (to rd) <40> t srdid (1.5 + w + w d )t ? 21 ns off-page rd low-level width <171> t wrdl (1.5 + w + w d )t ? 10 ns rd high-level width <172> t wrdh (0.5 + w as )t ? 10 ns data input hold time (from rd ) <45> t hrdid 0 ns delay time from rd to data output <46> t drdod (0.5 + i)t ? 10 ns on-page rd low-level width <173> t wordl (1.5 + w + w pr )t ? 10 ns on-page data input setup time (to address) <64> t soaid (2 + w + w pr + w as )t ? 21 ns on-page data input setup time (to rd) <174> t sordid (1.5 + w + w pr )t ? 21 ns remarks 1. t = t cyk1 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. w pr : wait count based on the prc register 5. i: count of idle states insert ed when a write cycle follows a read cycle 6. w as : address setup wait count based on the asc register 7. maintain at least one of the data input hold times t hkid or t hrdid
chapter 15 electrical specifications user's manual u14980ej2v1ud 431 (b) 8-bit bus width (byte access), 16-bit bus width (byte/halfword access) (2/2) csn (output) clkout (output) t1 tdw tw t2 <39> <171> <35> <33> <32> <32> <33> d0 to d15 (i/o) uwr, lwr (output) rd (output) wait (input) <34> to1 tprw tw to2 <64> <34> <35> <45> <33> <32> <33> <32> tasw tasw <46> address (output) note <40> <172> <173> <174> note on-page and off-page addresses are as follows. prc register ma6 ma5 ma4 ma3 on-page address off-page address 0 0 0 0 a0 to a2 a3 to a24 0 0 0 1 a0 to a3 a4 to a24 0 0 1 1 a0 to a4 a5 to a24 0 1 1 1 a0 to a5 a6 to a24 1 1 1 1 a0 to a6 a7 to a24 remarks 1. this is the timing for the following case. wait count based on the dwc0 and dwc1 registers (tdw): 1 wait count based on the prc register (tprw): 1 wait count based on the asc register (tasw): 1 2. broken lines indicate high impedance. 3. n = 0, 3, 4, 7
chapter 15 electrical specifications user's manual u14980ej2v1ud 432 ( 6) sdram access timing (a) read timing (sdram access) (1/2) parameter symbol conditions min. max. unit address delay time (from sdclk ) <126> t dka2 2 13 ns csn delay time (from sdclk ) <128> t dkcs 2 13 ns sdras delay time (from sdclk ) <129> t dkras 2 13 ns sdcas delay time (from sdclk ) <130> t dkcas 2 13 ns udqm, ldqm delay time (from sdclk ) <131> t dkdqm 2 13 ns sdcke delay time (from sdclk ) <132> t dkcke 2 13 ns data input setup time (at sdram read, to sdclk ) <133> t sdrmk 8 ns data input hold time (at sdram read, from sdclk ) <134> t hkdrm 0 ns delay time from sdclk to data output <135> t dsdod (1 + i)t ? 5 ns remarks 1. t = t cyk2 2. i: idle state count 3. n = 3, 4
chapter 15 electrical specifications user's manual u14980ej2v1ud 433 (a) read timing (sdram access) (2/2) sdclk (output) tw tact tbcw tread tlate tlate <126> csn (output) sdcas (output) sdras (output) we (output) ldqm (output) udqm (output) d0 to d15 (i/o) sdcke (output) rd (output) a10 (output) a0 to a9 (output) <126> <126> <126> <128> <126> <126> <126> <126> <126> <129> <130> <131> <131> <131> <133> <134> <128> <129> <130> <131> <126> data address bank address (output) <135> bank address and addresses other than a10 and a0 to a9 (output) address column address <132> <132> address address bank address row address row address remarks 1. wait count based on the bcw1n and bcw0n bi ts of the scrn register (tbcw): 2 2. broken lines indicate high impedance. 3. n = 3, 4
chapter 15 electrical specifications user's manual u14980ej2v1ud 434 (b) write timing (sdram access) (1/2) parameter symbol conditions min. max. unit address delay time (from sdclk ) <126> t dka2 2 13 ns csn delay time (from sdclk ) <128> t dkcs 2 13 ns sdras delay time (from sdclk ) <129> t dkras 2 13 ns sdcas delay time (from sdclk ) <130> t dkcas 2 13 ns udqm, ldqm delay time (from sdclk ) <131> t dkdqm 2 13 ns sdcke delay time (from sdclk ) <132> t dkcke 2 13 ns we delay time (from sdclk ) <136> t dkwe 2 13 ns data output delay time (from sdclk ) <137> t dkdt 2 13 ns data float delay time (from sdclk ) <138> t hzkdt 2 13 ns remark n = 3, 4
chapter 15 electrical specifications user's manual u14980ej2v1ud 435 (b) write timing (sdram access) (2/2) tw tact tbcw twr1 twr2 twr3 <126> <126> <126> <126> <128> <126> <126> <126> <126> <126> <129> <130> <136> <131> <131> <131> <137> <138> <128> <129> <130> <136> <131> <126> <132> <132> sdclk (output) csn (output) sdcas (output) sdras (output) we (output) ldqm (output) udqm (output) d0 to d15 (i/o) sdcke (output) rd (output) a10 (output) a0 to a9 (output) bank address (output) bank address and addresses other than a10 and a0 to a9 (output) data address address address address column address bank address row address row address remarks 1. wait count based on the bcw1n and bcw0n bi ts of the scrn register (tbcw): 2 2. broken lines indicate high impedance. 3. n = 3, 4
chapter 15 electrical specifications user's manual u14980ej2v1ud 436 (7) dmac timing parameter symbol conditions min. max. unit dmarqn setup time (to clkout ) <139> t sdrk 8 ns <140> t hkdr1 after inactive (from clkout ) 3 ns dmarqn hold time <141> t hkdr2 until dmaakn ns second dma request disable timing in single transfer <142> t akdr 3t ns dmaakn output delay time (from clkout ) <143> t dkda 2 13 ns dmaakn output hold time (from clkout ) <144> t hkda 2 13 ns tc0 output delay time (from clkout ) <145> t hktc 2 13 ns tc0 output hold time (from clkout ) <146> t hktc 2 13 ns remarks 1. t = t cyk1 2. n = 0, 1 clkout (output) <141> <143> <144> <145> <139> dmaakn (output) dmarqn (input) tc0 (output) <142> <140> <146> remarks 1. the tc0 signal is out put in the write cycle. 2. n = 0, 1
chapter 15 electrical specifications user's manual u14980ej2v1ud 437 (8) bus hold timing (1/2) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) <147> t shrk 8 ns hldrq hold time (from clkout ) <148> t hkhr 3 ns delay time from clkout to hldak <149> t dkha 2 13 ns hldrq high-level width <150> t whqh t + 3 ns hldak low-level width <151> t whal t ? 11 ns delay time from hldak to bus float <152> t dkcf 0 ns delay time from hldak to bus output <153> t dhac 0 13 ns delay time from hldrq to hldak <154> t dhqha1 2t ns delay time from hldrq to hldak <155> t dhqha2 t 2t + 10 ns remark t = t cyk1
chapter 15 electrical specifications user's manual u14980ej2v1ud 438 (8) bus hold timing (2/2) clkout (output) ti d0 to d15 (i/o) <147> th th th ti t1 <148> <148> <147> <154> <149> <151> <155> <150> <149> <152> <153> a0 to a24 (output) address data hldrq (input) hldak (output) csn (output) rd (output) we (output) wait (input) <147> undefined remarks 1. broken lines indicate high impedance. 2. n = 0, 3, 4, 7
chapter 15 electrical specifications user's manual u14980ej2v1ud 439 (9) interrupt timing parameter symbol conditions min. max. unit nmi high-level width <156> t wnih 500 ns nmi low-level width <157> t wnil 500 ns intp0n high-level width <158> t wit0h 3t + 500 ns intp0n low-level width <159> t wit0l 3t + 500 ns intp1m high-level width <160> t wit1h 500 ns intp1m low-level width <161> t wit1l 500 ns remarks 1. n = 00, 01, 10, 11 m = 00, 01, 10 2. t = t cyk1 <156> <157> nmi (input) <158> <159> intp0n (input) <160> <161> intp1m (input) remark n = 00, 01, 10, 11 m = 00, 01, 10 (10) rpu timing parameter symbol conditions min. max. unit ti0n0 high-level width <162> t wtih 3t + 500 ns ti0n0 low-level width <163> t wtil 3t + 500 ns remarks 1. n = 0, 1 2. t = t cyk1 <162> <163> ti0n0 (input) remark n = 0, 1
chapter 15 electrical specifications user's manual u14980ej2v1ud 440 (11) csi0, csi1 timing (1/3) (a) master mode parameter symbol conditions min. max. unit sckn cycle <164> t cysk1 output 320 ns sckn high-level width <165> t wsk1h output 0.5t cysk1 ? 20 ns sckn low-level width <166> t wsk1l output 0.5t cysk1 ? 20 ns sin setup time (to sckn ) 30 ns sin setup time (to sckn ) <167> t ssisk 30 ns sin hold time (from sckn ) 30 ns sin hold time (from sckn ) <168> t hsksi 30 ns son output delay time (from sckn ) 30 ns son output delay time (from sckn ) <169> t dskso 30 ns son output hold time (from sckn ) 0.5t cysk1 ? 5 ns son output hold time (from sckn ) <170> t hskso 0.5t cysk1 ? 5 ns remark n = 0, 1 (b) slave mode parameter symbol conditions min. max. unit sckn cycle <164> t cysk1 input 200 ns sckn high-level width <165> t wsk1h input 90 ns sckn low-level width <166> t wsk1l input 90 ns sin setup time (to sckn ) 50 ns sin setup time (to sckn ) <167> t ssisk 50 ns sin hold time (from sckn ) 50 ns sin hold time (from sckn ) <168> t hsksi 50 ns son output delay time (from sckn ) 50 ns son output delay time (from sckn ) <169> t dskso 50 ns son output hold time (from sckn ) t wsk1h ns son output hold time (from sckn ) <170> t hskso t wsk1h ns remark n = 0, 1
chapter 15 electrical specifications user's manual u14980ej2v1ud 441 (11) csi0 to csi1 timing (2/3) (c) timing when ckpn, dapn bits of csicn register = 00 <164> <166> <165> <167> <168> <169> <170> sin (input) son (output) sckn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0, 1 (d) timing when ckpn, dapn bits of csicn register = 01 <167> <168> <170> sin (input) son (output) input data output data <164> <166> <165> sckn (i/o) <169> remarks 1. broken lines indicate high impedance. 2. n = 0, 1
chapter 15 electrical specifications user's manual u14980ej2v1ud 442 (11) csi0, csi1 timing (3/3) (e) timing when ckpn, dapn bits of csicn register = 10 <164> <166> <165> <167> <168> <169> <170> sin (input) son (output) sckn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0, 1 (f) timing when ckpn, dapn bits of csicn register = 11 <167> <168> <170> sin (input) son (output) input data output data <164> <166> <165> sckn (i/o) <169> remarks 1. broken lines indicate high impedance. 2. n = 0, 1
chapter 15 electrical specifications user's manual u14980ej2v1ud 443 a/d converter characteristics (t a = ? 40 to +85 c, v dd = av dd = 3.0 to 3.6 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution ? 10 bit overall error note 1 ? 0.49 %fsr quantization error ? 1/2 lsb conversion time t conv 5 10 s sampling time t samp conversion clock note 2 /6 ns zero-scale error note 1 ? 0.49 %fsr full-scale error note 1 ? 0.49 %fsr integral linearity error note 3 ? 4 lsb differential linearity error note 3 ? 4 lsb analog input voltage v wasn ? 0.3 av ref + 0.3 v av ref input voltage av ref av ref = av dd 3.0 3.6 v av dd supply current ai dd 10 ma notes 1. excluding quantization error ( 0.05 %fsr) 2. conversion clock is the number of clocks set by the adm1 resister. 3. excluding quantization error ( 0.5 lsb) remark lsb: least significant bit fsr: full scale range % fsr is the ratio to the full-scale value.
444 user's manual u14980ej2v1ud chapter 16 package drawing 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
445 user's manual u14980ej2v1ud chapter 17 recommended soldering conditions the v850e/ma2 should be soldered and mount ed under the following recommended conditions. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 17-1. surface mounting type solderi ng conditions pd703108gc-8eu-a : 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 wave soldering for details, consult an nec electronics sales representative. ? partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remarks 1. products with -a at the end of the part number are lead-free products. 2. for soldering methods and conditions other than those recommended above, consult an nec electronics sales representative. 3. for soldering conditions for the pd703108gc-8eu have not been determined.
446 user's manual u14980ej2v1ud appendix a notes on target system design the following shows a diagram of the connection condi tions between the in-circuit emulator option board and conversion connector. design your system making allowanc es for conditions such as the form of parts mounted on the target system as shown below. figure a-1. 100-pin plastic lqfp (fine pitch) (14 14) side view 206.26 mm in-circuit emulator option board conversion connector ie-703107-mc-em1 in-circuit emulator ie-v850e-mc-a target system nqpack100sd yqpack100sd note yqguide vp-v850e/ma1-ma2 note yqsocket100sdn (sold separately ) can be inserted here to adjust the height (height: 3.2 mm). top view ie-703107-mc-em1 ie-v850e-mc-a target system yqpack100sd, nqpack100sd, yqguide 11.5 mm 36.0 mm 13.5 mm connection condition diagram connect to ie-v850e-mc-a. ie-703107-mc-em1 75 mm 50 mm 16.5 mm 47.21 mm 36.0 mm 25.8 mm pin 1 position vp-v850e/ma1-ma2 yqpack100sd nqpack100sd target system
447 user's manual u14980ej2v1ud appendix b cautions b.1 restriction on page rom access b.1.1 description in systems connecting multiple page roms to multiple di fferent csn spaces, when the page rom of a different csn space is continuously accessed immediately after a pag e rom is accessed, if the value of the former address and that of the latter address are on the sa me page of the page rom, even if the two csn spaces are different, it is taken as access of the same page of the page rom, and the on -page cycle is issued for the latter access (n = 0, 3, 4, 7). as a result, the data access time of the latter access is insufficient, making it impossible to perform normal reading. caution the page rom has a page access function and includes memo ry that allows high-speed continuous access on the page (refer to figure b-1). for example, if the 8xxxxx2h address of the cs4 space is accessed immediately after the 0xxxxx0h address of the cs0 space is accessed, the on-page cycl e is executed for 8xxxxx2h. (refer to figure b-1 .) figure b-1. example of structure of memory map with error page rom (b) page rom (a) area 3 area 2 area 1 area 0 fffffffh 81fffffh 8000000h 01fffffh 0000000h 0000000h c000000h bffffffh 8000000h 7ffffffh 4000000h 3ffffffh cs4 01fffffh 0000000h 01fffffh 0000000h cs0 addresses of a0 to a25 examples of conditions under which an error does not occur are shown below. ? rom with page mode is not used. ? only one rom with page mode is used. ? the addresses of a0 to a25 do not overl ap in all the roms with page mode used.
appendix b cautions 448 user's manual u14980ej2v1ud b.1.2 countermeasures when using several page roms, arrange the page roms so that the addresses of a0 to a25 do not overlap. for example, when arranging two 2 mb page roms in different csn spaces, set one page rom to 0000000h to 01fffffh, and the other page rom to f800000h to f9fffffh. (refer to figure b-2 .) figure b-2. example of structur e of memory map preventing error page rom (b) page rom (a) area 3 area 2 area 1 area 0 fffffffh f9fffffh f800000h 39fffffh 3800000h 0000000h c000000h bffffffh 8000000h 7ffffffh 4000000h 3ffffffh 01fffffh 0000000h 01fffffh 0000000h cs0 addresses of a0 to a25 cs7
user's manual u14980ej2v1ud 449 appendix c register index (1/5) register symbol register name unit page adcr0 a/d conversion result register 0 (10 bits) adc 340 adcr0h a/d conversion result register 0h (8 bits) adc 340 adcr1 a/d conversion result register 1 (10 bits) adc 340 adcr1h a/d conversion result register 1h (8 bits) adc 340 adcr2 a/d conversion result register 2 (10 bits) adc 340 adcr2h a/d conversion result register 2h (8 bits) adc 340 adcr3 a/d conversion result register 3 (10 bits) adc 340 adcr3h a/d conversion result register 3h (8 bits) adc 340 adic interrupt control register intc 212 adm0 a/d converter mode register 0 adc 336 adm1 a/d converter mode register 1 adc 338 adm2 a/d converter mode register 2 adc 339 asc address setup wait control register bcu 96 asif0 asynchronous serial interface tr ansmission status register 0 uart0 297 asif1 asynchronous serial interface tr ansmission status register 1 uart1 297 asim0 asynchronous serial interface mode register 0 uart0 293 asim1 asynchronous serial interface mode register 1 uart1 293 asis0 asynchronous serial interface status register 0 uart0 296 asis1 asynchronous serial interface status register 1 uart1 296 bcc bus cycle control register bcu 99 bct0 bus cycle type configuration register 0 bcu 77 bct1 bus cycle type configuration register 1 bcu 77 bec endian configuration register bcu 80 brgc0 baud rate generator control register 0 brg0 315 brgc1 baud rate generator control register 1 brg1 315 bsc bus size configuration register bcu 79 ccc00 capture/compare register c00 rpu 258 ccc01 capture/compare register c01 rpu 258 ccc10 capture/compare register c10 rpu 258 ccc11 capture/compare register c11 rpu 258 ckc clock control register cg 234 cksr0 clock select register 0 uart0 314 cksr1 clock select register 1 uart1 314 cmd0 compare register d0 rpu 282 cmd1 compare register d1 rpu 282 cmd2 compare register d2 rpu 282 cmd3 compare register d3 rpu 282 cmicd0 interrupt control register intc 212
appendix c register index user's manual u14980ej2v1ud 450 (2/5) register symbol register name unit page cmicd1 interrupt control register intc 212 cmicd2 interrupt control register intc 212 cmicd3 interrupt control register intc 212 csc0 chip area selection control register 0 bcu 76 csc1 chip area selection control register 1 bcu 76 csic0 clocked serial interface cl ock selection register 0 csi0 324 csic1 clocked serial interface cl ock selection register 1 csi1 324 csiic0 interrupt control register intc 212 csiic1 interrupt control register intc 212 csim0 clocked serial interf ace mode register 0 csi0 322 csim1 clocked serial interf ace mode register 1 csi1 322 dadc0 dma addressing control register 0 dmac 164 dadc1 dma addressing control register 1 dmac 164 dadc2 dma addressing control register 2 dmac 164 dadc3 dma addressing control register 3 dmac 164 dbc0 dma byte count register 0 dmac 163 dbc1 dma byte count register 1 dmac 163 dbc2 dma byte count register 2 dmac 163 dbc3 dma byte count register 3 dmac 163 dchc0 dma channel control register 0 dmac 166 dchc1 dma channel control register 1 dmac 166 dchc2 dma channel control register 2 dmac 166 dchc3 dma channel control register 3 dmac 166 dda0h dma destination address register 0h dmac 161 dda0l dma destination address register 0l dmac 162 dda1h dma destination address register 1h dmac 161 dda1l dma destination address register 1l dmac 162 dda2h dma destination address register 2h dmac 161 dda2l dma destination address register 2l dmac 162 dda3h dma destination address register 3h dmac 161 dda3l dma destination address register 3l dmac 162 ddis dma disable status register dmac 168 dmaic0 interrupt control register intc 212 dmaic1 interrupt control register intc 212 dmaic2 interrupt control register intc 212 dmaic3 interrupt control register intc 212 drst dma restart register dmac 168 dsa0h dma source address register 0h dmac 159 dsa0l dma source address register 0l dmac 160 dsa1h dma source address register 1h dmac 159
appendix c register index user's manual u14980ej2v1ud 451 (3/5) register symbol register name unit page dsa1l dma source address register 1l dmac 160 dsa2h dma source address register 2h dmac 159 dsa2l dma source address register 2l dmac 160 dsa3h dma source address register 3h dmac 159 dsa3l dma source address register 3l dmac 160 dtfr0 dma trigger factor register 0 dmac 170 dtfr1 dma trigger factor register 1 dmac 170 dtfr2 dma trigger factor register 2 dmac 170 dtfr3 dma trigger factor register 3 dmac 170 dtoc dma terminal count output control register dmac 169 dwc0 data wait control register 0 bcu 94 dwc1 data wait control register 1 bcu 94 imr0 interrupt mask register 0 intc 213 imr1 interrupt mask register 1 intc 213 imr2 interrupt mask register 2 intc 213 imr3 interrupt mask register 3 intc 213 intm0 external interrupt mode register 0 intc 203 intm1 external interrupt mode register 1 intc 216 intm2 external interrupt mode register 2 intc 216 ispr in-service priority register intc 215 lockr lock register cpu 237 ovic00 interrupt control register intc 212 ovic01 interrupt control register intc 212 p0 port 0 port 381 p00ic0 interrupt control register intc 212 p00ic1 interrupt control register intc 212 p01ic0 interrupt control register intc 212 p01ic1 interrupt control register intc 212 p1 port 1 port 384 p10ic0 interrupt control register intc 212 p10ic1 interrupt control register intc 212 p11ic0 interrupt control register intc 212 p2 port 2 port 386 p4 port 4 port 388 p7 port 7 port 391 pah port ah port 394 pal port al port 391 pbd port bd port 407 pcd port cd port 404 pcm port cm port 402
appendix c register index user's manual u14980ej2v1ud 452 (4/5) register symbol register name unit page pcs port cs port 398 pct port ct port 400 pdl port dl port 396 pfc0 port 0 function control register port 383 pfc2 port 2 function control register port 387 pfc4 port 4 function control register port 390 pfccd port cd function control register port 406 phcmd peripheral command register cpu 233 phs peripheral status register cpu 236 pm0 port 0 mode register port 381 pm1 port 1 mode register port 384 pm2 port 2 mode register port 386 pm4 port 4 mode register port 388 pmah port ah mode register port 395 pmal port al mode register port 393 pmbd port bd mode register port 407 pmc0 port 0 mode control register port 382 pmc1 port 1 mode control register port 385 pmc2 port 2 mode control register port 387 pmc4 port 4 mode control register port 389 pmcah port ah mode control register port 395 pmcal port al mode control register port 393 pmcbd port bd mode control register port 408 pmccd port cd mode control register port 405 pmccm port cm mode control register port 403 pmccs port cs mode control register port 399 pmcct port ct mode control register port 401 pmcd port cd mode register port 404 pmcdl port dl mode control register port 397 pmcm port cm mode register port 402 pmcs port cs mode register port 398 pmct port ct mode register port 400 pmdl port dl mode register port 396 prc page rom configuration register memc 123 prcmd command register cpu 240 psc power save control register cpu 241 psmr power save mode register cpu 240 rfs3 sdram refresh control register 3 memc 147 rfs4 sdram refresh control register 4 memc 147 rxb0 receive buffer register 0 uart0 298
appendix c register index user's manual u14980ej2v1ud 453 (5/5) register symbol register name unit page rxb1 receive buffer register 1 uart1 298 scr3 sdram configuration register 3 memc 131 scr4 sdram configuration register 4 memc 131 seic0 interrupt control register intc 212 seic1 interrupt control register intc 212 sesc0 valid edge selection register c0 intc 218, 264 sesc1 valid edge selection register c1 intc 218, 264 sio0 serial i/o shift register 0 csi0 326 sio1 serial i/o shift register 1 csi1 326 sioe0 receive-only serial i/o shift register 0 csi0 326 sioe1 receive-only serial i/o shift register 1 csi1 326 sotb0 clocked serial interface tr ansmit buffer register 0 csi0 327 sotb1 clocked serial interface tr ansmit buffer register 1 csi1 327 sric0 interrupt control register intc 212 sric1 interrupt control register intc 212 stic0 interrupt control register intc 212 stic1 interrupt control register intc 212 tmc0 timer c0 rpu 256 tmc1 timer c1 rpu 256 tmcc00 timer mode control register c00 rpu 260 tmcc01 timer mode control register c01 rpu 262 tmcc10 timer mode control register c10 rpu 260 tmcc11 timer mode control register c11 rpu 262 tmcd0 timer mode control register d0 rpu 284 tmcd1 timer mode control register d1 rpu 284 tmcd2 timer mode control register d2 rpu 284 tmcd3 timer mode control register d3 rpu 284 tmd0 timer d0 rpu 281 tmd1 timer d1 rpu 281 tmd2 timer d2 rpu 281 tmd3 timer d3 rpu 281 txb0 transmit buffer register 0 uart0 299 txb1 transmit buffer register 1 uart1 299 vswc system wait control register bcu 72
user's manual u14980ej2v1ud 454 appendix d instruction set list d.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the remainders of division results and the higher order 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the conditions code sp stack pointer (sp) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list s 1-bit data that specifies a system register in the register list
appendix d instruction set list user's manual u14980ej2v1ud 455 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) half-word half word (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency).
appendix d instruction set list user's manual u14980ej2v1ud 456 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition name (cond) condition code (cccc) condition formula explanation v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry not lower (greater than or equal) z/e 0 0 1 0 z = 1 zero equal nz/ne 1 0 1 0 z = 0 not zero not equal nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) n 0 1 0 0 s = 1 negative p 1 1 0 0 s = 0 positive t 0 1 0 1 ? always (unconditional) sa 1 1 0 1 sat = 1 saturated lt 0 1 1 0 (s xor ov) = 1 less than signed ge 1 1 1 0 (s xor ov) = 0 greater than or equal signed le 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed gt 1 1 1 1 ((s xor ov) or z) = 0 greater than signed
appendix d instruction set list user's manual u14980ej2v1ud 457 d.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 r r r r r 0 1 0 010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 0 when conditions are satisfied 3 note 2 3 note 2 3 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,half-word)) 5 5 5 bit#3, disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 r r r r r 1 1 1 111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 r r r r r 0 1 0 011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 4 4 4 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 4 4 4 r r r r r
appendix d instruction set list user's manual u14980ej2v1ud 458 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (returned pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 4 4 4 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 3 3 3 jmp [reg1] 00000000011rrrrr pc gr[reg1] 4 4 4 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 3 3 3 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11
appendix d instruction set list user's manual u14980ej2v1ud 459 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,half- word)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-exend(disp16) gr[reg2] zero-extend(load-memory(adr,half-word) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-exend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 9 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 r r r r r 0 1 0 000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] reg1 reg2 reg3, reg3 r0 1 2 note 1 4 2 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 2 note 1 4 2 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 r r r r r 0 1 0 111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] reg1 reg2 reg3, reg3 r0 1 2 note 1 4 2 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 2 note 1 4 2 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3
appendix d instruction set list user's manual u14980ej2v1ud 460 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) gr[reg in list 12] load-memory(sp,word) sp sp+4 repeat 2 step above until a ll regs in list12 is loaded pc gr[reg1] n+2 note 4 note 1 7 n+2 note 4 note 1 7 n+2 note 4 note 1 7 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 4 4 4 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1
appendix d instruction set list user's manual u14980ej2v1ud 461 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,half- word)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,half- word)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],half-word) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], half-word) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1
appendix d instruction set list user's manual u14980ej2v1ud 462 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,half-word))) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (return pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 4 4 4 tst reg1,reg2 r r rr r0 01 01 1 r rrr r result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 4 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (a ccording to the number of wait states. also, if there are no wait states, n is the num ber of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower half word data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states).
appendix d instruction set list user's manual u14980ej2v1ud 463 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: lower 4 bits of imm9. 14. in the case of reg2 = reg3 (the lower 32 bits of the results are not written in the register) or reg3 = r0 (the higher 32 bits of the results are not wri tten in the register), shortened by 1 clock. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr : other t han 00000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8.
user's manual u14980ej2v1ud 464 appendix e index [a] a/d conversion result registers 0 to 3 .................... 340 a/d conversion result registers 0h to 3h ............... 340 a/d converter char acterist ics ................................. 362 a/d converter mode register 0 ............................... 336 a/d converter mode register 1 ............................... 338 a/d converter mode register 2 ............................... 339 a/d converter operatio n ......................................... 342 a0 to a15 ................................................................. 45 a16 to a24 ............................................................... 44 ac characte ristic s .................................................. 418 adcr0 to adcr3 .................................................. 340 adcr0h to adcr3h ............................................. 340 address multiple x functi on ..................................... 129 address setup wait control re gister .......................... 96 address sp ace ......................................................... 56 adic ...................................................................... 212 adm0 ..................................................................... 336 adm1 ..................................................................... 338 adm2 ..................................................................... 339 ani0 to ani3 ............................................................ 40 applicat ions .............................................................. 27 area ......................................................................... 60 asc.......................................................................... 96 asif0, asi f1 ......................................................... 297 asim0, asi m1........................................................ 293 asis0, asi s1......................................................... 296 asynchronous serial interface mode registers 0, 1 .......................................................... 293 asynchronous serial interface status registers 0, 1 .......................................................... 296 asynchronous serial interface transmission status registers 0, 1 .......................................................... 297 asynchronous serial in terfaces 0, 1 ....................... 290 av dd ......................................................................... 46 av ref ....................................................................... 46 av ss ......................................................................... 46 [b] basic configurati on of time r c ................................ 255 basic configurati on of time r d ................................ 280 baud rate generator cont rol register s 0, 1 .............. 315 bcc ......................................................................... 99 bct0, bc t1............................................................. 77 bec.......................................................................... 80 block transfe r mode ............................................... 177 boundary operati on conditi ons .............................. 109 brg0, br g1 ......................................................... 313 brgc0, br gc1 .................................................... 315 bsc ......................................................................... 79 bus acce ss .............................................................. 79 bus contro l pins ....................................................... 74 bus cycle contro l regist er......................................... 99 bus cycle type configuratio n registers 0, 1 .............. 77 bus cycle type cont rol func tion ................................ 77 bus cycles in which wait function is valid ................. 98 bus hold f unction ................................................... 100 bus hold proc edure ................................................ 101 bus hold timing (sdra m) ...................................... 104 bus hold timing (sra m) ........................................ 102 bus priority orde r ................................................... 108 bus size configur ation regi ster................................. 79 bus sizing functi on................................................... 79 bus wid th ................................................................. 83 [c] capture/compare register s c00, 01, 10, 11 ........... 258 cautions (page rom acce ss) ............................... 447 ccc00, 01, 10, 11 ................................................. 258 chip area select ion control regi sters 0, 1................. 76 chip select cont rol func tion...................................... 76 ckc ....................................................................... 234 cksel ..................................................................... 45 cksr0, c ksr1 ..................................................... 314 clkout .................................................................. 41 clock control regist er ............................................. 234 clock select regi sters 0, 1...................................... 314 clocked serial interface clock selection registers 0, 1 .......................................................... 324 clocked serial interface mo de registers 0, 1 .......... 322 clocked serial interface transmit buffer registers 0, 1 .......................................................... 327 clocked serial inte rfaces 0, 1................................. 321 cmd0 to cmd3 ..................................................... 282 cmicd0 to cmicd3 .............................................. 212 command r egister ................................................. 240 compare match interrupt when in timer trigger mode........................................................... 359 compare register s d0 to d3 .................................. 282 conversion time ..................................................... 365 cpu address space................................................. 56 cpu register set ...................................................... 51
appendix e index user's manual u14980ej2v1ud 465 cs0, cs3, cs 4, cs 7 ............................................... 43 csc0, cs c1............................................................ 76 csi0, cs i1 ............................................................. 321 csic0, cs ic1 ........................................................ 324 csiic0, cs iic1 ...................................................... 212 csim0, cs im1 ....................................................... 322 cv dd ........................................................................ 46 cv ss ......................................................................... 46 [d] d0 to d15................................................................. 45 dadc0 to dadc3 .................................................. 164 data retension c haracterist ics ................................ 417 data s pace ............................................................. 109 data wait control registers 0, 1................................. 94 dbc0 to dbc3 ....................................................... 163 dc characteri stics.................................................. 416 dchc0 to dchc3 ................................................. 166 dda0h to dda3h .................................................. 161 dda0l to dd a3l................................................... 162 ddis ...................................................................... 168 debug tr ap ............................................................. 224 dedicated baud rate generators 0, 1...................... 313 description of pi n functi ons ...................................... 38 differential linea rity e rror ........................................ 364 direct m ode............................................................ 232 dma addressing control r egisters 0 to 3 ................ 164 dma bus st ates...................................................... 172 dma byte count regi sters 0 to 3............................. 163 dma channel control re gisters 0 to 3 ..................... 166 dma channel pr ioriti es........................................... 189 dma destination address r egisters 0h to 3h ......... 161 dma destination address registers 0l to 3l .......... 162 dma disable stat us regi ster ................................... 168 dma restart regist er............................................... 168 dma source address re gisters 0h to 3h ................ 159 dma source address re gisters 0l to 3l ................. 160 dma terminal count outpu t control re gister ............ 169 dma transfe r end ................................................... 196 dma transfer star t factor s ...................................... 190 dma trigger factor r egisters 0 to 3 ......................... 170 dmaak0, dm aak1 ................................................. 41 dmac bus cycle st ate transit ion ............................ 173 dmaic0 to dmaic3 ............................................... 212 dmarq0, dm arq1 ................................................ 38 drst ..................................................................... 168 dsa0h to dsa3h .................................................. 159 dsa0l to dsa3l ................................................... 160 dtfr0 to dtfr3 ...................................................170 dtoc ..................................................................... 169 dwc0, dw c1 .......................................................... 94 [e] edge detection function (non-maskable in terrupt ) ........................................203 electrical spec ificati ons .......................................... 414 endian configurat ion regi ster ....................................80 endian control functi on ............................................. 80 ep........................................................................... 221 exception stat us fl ag .............................................. 221 exception trap ........................................................222 external bus cycles dur ing dma tr ansfer ................188 external interrupt mode regist er 0 ..........................203 external interrupt m ode registers 1, 2.....................216 external memory expansio n .....................................64 external wait function ...............................................97 [f] forcible in terrupt .....................................................192 forcible te rminati on ................................................ 193 full-scale error ........................................................364 [h] halt m ode ............................................................ 243 hldak .....................................................................41 hldrq .....................................................................42 [i] id............................................................................215 idle m ode ............................................................. 245 idle state insert ion func tion.......................................99 illegal opcode def initio n ..........................................222 image .......................................................................57 imr0 to imr3 .........................................................213 input clock se lectio n ...............................................232 in-service priori ty regi ster .......................................215 integral linear ity erro r..............................................365 internal blo ck diagr am .............................................. 30 interrupt contro l regist er ......................................... 211 interrupt lat ency ti me ..............................................228 interrupt mask regi sters 0 to 3 ................................213 interrupt trigger mode select ion ..............................216 intm0 ..................................................................... 203 intm1, in tm2 ........................................................216 intp000, in tp001 ...................................................38 intp010, in tp011 ...................................................39 intp100, in tp101 ...................................................38
appendix e index user's manual u14980ej2v1ud 466 intp110 ................................................................... 39 ispr ....................................................................... 215 [l] lbe .......................................................................... 44 ldqm ....................................................................... 43 list of pin functi on .................................................... 33 lock regi ster ........................................................... 237 lockr ................................................................... 237 lwr ......................................................................... 42 [m] maskable interrupt status flag ................................ 215 maskable inte rrupts ................................................ 204 maximum response time for dma transfer reques t ................................................................... 194 memory block functi on ............................................. 75 memory map ............................................................ 59 mode0 to mode2 ................................................... 45 multiple interrupt se rvicing co ntrol .......................... 226 [n] next address setti ng functi on ................................. 189 nmi .......................................................................... 39 noise elimination (ma skable inte rrupt) ................... 216 noise elimination (non -maskable inte rrupt) ............ 203 non-maskable interr upt .......................................... 199 non-maskable interrupt status flag ......................... 203 notes on target system des ign............................... 446 np .......................................................................... 203 number of ac cess clo cks ......................................... 79 [o] on-chip un its ............................................................ 30 one-time transfer during single transfer via dmarq0, dmarq1 signal s .................................. 195 on-page/off-pa ge judgmen t ................................... 121 operation in a/d trigger mode................................ 348 operation in powe r save mode .............................. 101 operation in st andby m ode .................................... 358 operation in time r trigger mode .............................. 351 operation mode and trigger mode ......................... 343 operation mode s pecificat ion ................................... 55 operation modes ...................................................... 55 ordering info rmation ................................................ 27 overall e rror ........................................................... 362 ovic00, ov ic01 .................................................... 212 [p] p0 .......................................................................... 381 p00ic0, p 00ic1 ..................................................... 212 p01 to p05 ............................................................... 38 p01ic0, p 01ic1 ..................................................... 212 p1 .......................................................................... 384 p10ic0, p 10ic1 ..................................................... 212 p11, p1 2 .................................................................. 39 p11ic0 ................................................................... 212 p2 .......................................................................... 386 p20, p2 4 .................................................................. 39 p4 .......................................................................... 388 p40 to p45 ............................................................... 40 p7 .......................................................................... 391 p70 to p73 ............................................................... 40 package dr awing ................................................... 444 page rom ac cess................................................. 124 page rom configurat ion regi ster ........................... 123 page rom co nnection ........................................... 120 page rom cont roller ............................................. 119 pah ....................................................................... 394 pah0 to pah8 ......................................................... 44 pal........................................................................ 391 pal0 to pal15 ........................................................ 45 pbd ....................................................................... 407 pbd0, pbd 1 ............................................................ 41 pcd ....................................................................... 404 pcd0 to pcd3......................................................... 43 pcm ....................................................................... 402 pcm0 to pcm4 ........................................................ 41 pcs ....................................................................... 398 pcs0, pcs3, pc s4, pc s7 ..................................... 43 pct ....................................................................... 400 pct0, pct1, pc t4, pct5 ...................................... 42 pdl ........................................................................ 396 pdl0 to pdl15........................................................ 45 periods in which interrupts are not acknowle dged ........................................................ 229 peripheral comm and regist er................................. 233 peripheral i/o register s ............................................ 66 peripheral stat us regi ster ....................................... 236 pfc0 ..................................................................... 383 pfc2 ..................................................................... 387 pfc4 ..................................................................... 390 pfccd .................................................................. 406 phcmd ................................................................. 233 phs ....................................................................... 236 pin configur ation ...................................................... 28
appendix e index user's manual u14980ej2v1ud 467 pin i/o circ uits .......................................................... 49 pin i/o circuits and recommended connection of unused pi ns ............................................................. 47 pin stat us ................................................................. 37 pll lock up ............................................................. 237 pll mo de .............................................................. 233 pm0 ....................................................................... 381 pm1 ....................................................................... 384 pm2 ....................................................................... 386 pm4 ....................................................................... 388 pmah .................................................................... 395 pmal ..................................................................... 393 pmbd .................................................................... 407 pmc0 ..................................................................... 382 pmc1 ..................................................................... 385 pmc2 ..................................................................... 387 pmc4 ..................................................................... 389 pmcah .................................................................. 395 pmcal .................................................................. 393 pmcbd .................................................................. 408 pmccd .................................................................. 405 pmccm ................................................................. 403 pmccs .................................................................. 399 pmcct .................................................................. 401 pmcd .................................................................... 404 pmcdl .................................................................. 397 pmcm .................................................................... 402 pmcs .................................................................... 398 pmct ..................................................................... 400 pmdl ..................................................................... 396 port 0 ..................................................................... 381 port 0 function c ontrol regi ster ............................... 383 port 0 mode cont rol regi ster ................................... 382 port 0 mode regist er .............................................. 381 port 1 ..................................................................... 384 port 1 mode cont rol regi ster ................................... 385 port 1 mode regist er .............................................. 384 port 2 ..................................................................... 386 port 2 function c ontrol regi ster ............................... 387 port 2 mode cont rol regi ster ................................... 387 port 2 mode regist er .............................................. 386 port 4 ..................................................................... 388 port 4 function c ontrol regi ster ............................... 390 port 4 mode cont rol regi ster ................................... 389 port 4 mode regist er .............................................. 388 port ah .................................................................. 394 port ah mode cont rol regi ster ................................ 395 port ah mode regist er ........................................... 395 port al ................................................................... 391 port al mode cont rol regi ster .................................393 port al mode regist er............................................. 393 port bd................................................................... 407 port bd mode cont rol regi ster ................................408 port bd mode regist er ............................................ 407 port cd................................................................... 404 port cd function c ontrol regi ster .............................406 port cd mode cont rol regi ster ................................405 port cd mode regist er............................................ 404 port cm .................................................................. 402 port cm mode cont rol regi ster ................................403 port cm mode regist er ........................................... 404 port confi guratio n ...................................................367 port cs................................................................... 398 port cs mode cont rol regi ster ................................399 port cs mode regist er ............................................ 398 port ct ................................................................... 400 port ct mode cont rol regi ster ................................401 port ct mode regist er ............................................ 400 port dl ................................................................... 396 port dl mode cont rol regi ster .................................397 port dl mode regist er ............................................ 396 power save contro l .................................................238 power save cont rol regi ster ....................................241 power save m ode regist er...................................... 240 prc ........................................................................123 prcmd ..................................................................240 precautions (a/d conver ter) ...................................358 precautions (dma) .................................................196 precautions (t imer c).............................................. 279 precautions (t imer d).............................................. 288 precautions (uart) ...............................................320 prescaler unit .........................................................230 priorities of mask able interr upts .............................207 program regist er se t .................................................52 program sp ace .......................................................109 programmable wait functi on ..................................... 94 prs ........................................................................230 psc ........................................................................ 241 psmr ..................................................................... 240 [q] quantization error ...................................................363 [r] rd ............................................................................ 43 receive buffer regi sters 0, 1...................................298
appendix e index user's manual u14980ej2v1ud 468 receive-only serial i/o sh ift register s 0, 1 .............. 326 recommended o scillato r........................................ 415 recommended solder ing condit ions ...................... 445 recommended use of address s pace ...................... 65 refresh contro l functi on ......................................... 147 refr q..................................................................... 42 relationship between programmable wait and external wait ............................................................. 97 reset ..................................................................... 46 reset func tions ...................................................... 409 resoluti on .............................................................. 362 rfs3, rf s4........................................................... 147 romc .................................................................... 119 rxb0, r xb1 .......................................................... 298 rxd0, rx d1 ............................................................ 40 [s] sampling time ........................................................ 365 sck0, sc k1 ............................................................ 40 scr3, s cr4 .......................................................... 131 sdcas ..................................................................... 44 sdcke ..................................................................... 44 sdclk ..................................................................... 44 sdram a ccess ...................................................... 133 sdram configuration registers 3, 4 ....................... 131 sdram con nection ................................................ 128 sdram cont roller .................................................. 128 sdram initializa tion seque nce .............................. 154 sdram refresh control registers 3, 4..................... 147 sdras ..................................................................... 44 securing oscillation stabilizati on time ..................... 251 seic0, sei c1 ........................................................ 212 self-refresh cont rol func tion ................................... 152 serial i/o shift r egisters 0, 1 ................................... 326 sesc0, sesc1 .............................................. 218, 264 si0, si 1 .................................................................... 40 single transfe r mode .............................................. 174 single-step tran sfer m ode ...................................... 176 sio0, s io1............................................................. 326 sioe0, s ioe1 ........................................................ 326 so0, so1................................................................. 40 software exce ption ................................................. 219 software stop mode ............................................ 248 sotb0, so tb1...................................................... 327 specific re gister s...................................................... 72 sram conn ection .................................................. 111 sram, external rom, external i/o access ............ 113 sram, external rom, ex ternal i/o interface.......... 110 sric0, sr ic1 ........................................................ 212 stic0, st ic1 ........................................................ 212 stopping conversi on operatio n .............................. 358 switching between uart and csi modes ............ 289 system configuration example (csi0, sci1).......... 332 system regist er set .................................................. 53 system wait cont rol regi ster ..................................... 72 [t] tbc ....................................................................... 253 tc0.......................................................................... 39 terminal count output upon dma transfer end ...... 191 ti000 ....................................................................... 38 ti010 ....................................................................... 39 time base c ounter ................................................. 253 timer c .................................................................. 254 timer c oper ation .................................................. 265 timer d .................................................................. 280 timer d oper ation .................................................. 286 timer mode control regi sters c00, c10 ................. 260 timer mode control regi sters c01, c11 ................. 262 timer mode control regi sters d0 to d3 .................. 284 timer trigger interv al.............................................. 358 timers c0 , c1 ........................................................ 256 timers d0 to d3 ..................................................... 281 times related to dma trans fer ............................... 194 tmc0, tm c1 ......................................................... 256 tmcc00, tm cc10 ................................................ 260 tmcc01, tm cc11 ................................................ 262 tmcd0 to tmcd3 ................................................. 284 tmd0 to tmd3 ...................................................... 281 to00 ........................................................................ 38 transfer m odes ...................................................... 174 transfer obj ect ....................................................... 188 transfer type and tr ansfer ob ject ........................... 188 transmit buffer regi sters 0, 1 ................................. 299 two-cycle tr ansfer ................................................... 78 txb0, t xb1........................................................... 299 txd0, tx d1 ............................................................ 40 types of bus stat es................................................ 172 [u] uart0, ua rt1 ..................................................... 290 ube ......................................................................... 44 udqm ...................................................................... 43 uwr ........................................................................ 42
appendix e index user's manual u14980ej2v1ud 469 [v] valid edge selection regi sters c0, c1 ............ 218, 264 v dd ........................................................................... 46 v ss ........................................................................... 46 vswc ...................................................................... 72 [w] wait........................................................................ 41 wait func tion .............................................................94 we............................................................................43 wrap-around of cpu address s pace........................58 [x] x1, x2 .......................................................................46 [z] zero-scale error ......................................................363

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